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Differential D37124

AMDGPU: Correct operand types for v_mad_mix*
ClosedPublic

Authored by arsenm on Aug 24 2017, 3:36 PM.

Details

Reviewers
dp
Summary

These aren't really packed instructions, so the default
op_sel_hi should be 0 since this indicates a conversion.
The operand types are scalar values that behave similar
to an f16 scalar that may be converted to f32.




Doesn't change the default printing for op_sel_hi, just

the parsing.



Is there a script to update test/MC/AMDGPU/gfx9_asm_all.s? I got tired of manually updating all of the cases in it so it fails now.
Diff Detail
Event Timeline
arsenm created this revision.Aug 24 2017, 3:36 PM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others.  ·  View Herald TranscriptAug 24 2017, 3:36 PM
dp accepted this revision.Aug 26 2017, 2:01 AM
Looks good, except for minor issues.



Regarding gfx9_asm_all.s: you should not update it,  just delete all offending tests. The file will be updated by a test generator later.
lib/Target/AMDGPU/AMDGPU.td


718
unused


lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp


4275
That would be nice. Maybe by a separate change?
This revision is now accepted and ready to land.Aug 26 2017, 2:01 AM
arsenm closed this revision.Aug 30 2017, 3:20 PM
r312179
Revision Contents
PathSize
lib/
Target/
AMDGPU/
3 lines
AsmParser/
24 lines
1 line
20 lines
7 lines
test/
MC/
AMDGPU/
82 lines
58 lines
Diff 112623
lib/Target/AMDGPU/AMDGPU.td
Show First 20 Lines • Show All 708 Lines • ▼ Show 20 Linesdef HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,

  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;




def HasDPP : Predicate<"Subtarget->hasDPP()">,
def HasDPP : Predicate<"Subtarget->hasDPP()">,

  AssemblerPredicate<"FeatureDPP">;
  AssemblerPredicate<"FeatureDPP">;




def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,

  AssemblerPredicate<"FeatureIntClamp">;
  AssemblerPredicate<"FeatureIntClamp">;




def HasMadMix : Predicate<"Subtarget->hasMadMixInsts()">,

  AssemblerPredicate<"FeatureGFX9Insts">;

dpUnsubmitted
Not Done
ReplyInline Actions
unused
dp: unused


class PredicateControl {
class PredicateControl {

  Predicate SubtargetPredicate;
  Predicate SubtargetPredicate;

  Predicate SIAssemblerPredicate = isSICI;
  Predicate SIAssemblerPredicate = isSICI;

  Predicate VIAssemblerPredicate = isVI;
  Predicate VIAssemblerPredicate = isVI;

  list<Predicate> AssemblerPredicates = [];
  list<Predicate> AssemblerPredicates = [];

  Predicate AssemblerPredicate = TruePredicate;
  Predicate AssemblerPredicate = TruePredicate;

  list<Predicate> OtherPredicates = [];
  list<Predicate> OtherPredicates = [];

  list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
  list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],

Show All 14 Lines
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Show First 20 Lines • Show All 1,068 Lines • ▼ Show 20 Linespublic:

  AMDGPUOperand::Ptr defaultOffsetS13() const;
  AMDGPUOperand::Ptr defaultOffsetS13() const;




  OperandMatchResultTy parseOModOperand(OperandVector &Operands);
  OperandMatchResultTy parseOModOperand(OperandVector &Operands);




  void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
  void cvtVOP3(MCInst &Inst, const OperandVector &Operands,

               OptionalImmIndexMap &OptionalIdx);
               OptionalImmIndexMap &OptionalIdx);

  void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
  void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);

  void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
  void cvtVOP3(MCInst &Inst, const OperandVector &Operands);

  void cvtVOP3PImpl(MCInst &Inst, const OperandVector &Operands,

                    bool IsPacked);

  void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
  void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);

  void cvtVOP3P_NotPacked(MCInst &Inst, const OperandVector &Operands);




  void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
  void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);




  void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
  void cvtMIMG(MCInst &Inst, const OperandVector &Operands,

               bool IsAtomic = false);
               bool IsAtomic = false);

  void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
  void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);




  OperandMatchResultTy parseDPPCtrl(OperandVector &Operands);
  OperandMatchResultTy parseDPPCtrl(OperandVector &Operands);

▲ Show 20 Lines • Show All 3,163 Lines • ▼ Show 20 Linesvoid AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,

  }
  }

}
}




void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {

  OptionalImmIndexMap OptionalIdx;
  OptionalImmIndexMap OptionalIdx;

  cvtVOP3(Inst, Operands, OptionalIdx);
  cvtVOP3(Inst, Operands, OptionalIdx);

}
}




void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
void AMDGPUAsmParser::cvtVOP3PImpl(MCInst &Inst,

                                   const OperandVector &Operands,

                                   bool IsPacked) {

  OptionalImmIndexMap OptIdx;
  OptionalImmIndexMap OptIdx;




  cvtVOP3(Inst, Operands, OptIdx);
  cvtVOP3(Inst, Operands, OptIdx);




  // FIXME: This is messy. Parse the modifiers as if it was a normal VOP3
  // FIXME: This is messy. Parse the modifiers as if it was a normal VOP3

  // instruction, and then figure out where to actually put the modifiers
  // instruction, and then figure out where to actually put the modifiers

  int Opc = Inst.getOpcode();
  int Opc = Inst.getOpcode();




  addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);
  addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);




  int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);
  int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);

  if (OpSelHiIdx != -1) {
  if (OpSelHiIdx != -1) {

    addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi, -1);
    // TODO: Should we change the printing to match?

dpUnsubmitted
Not Done
ReplyInline Actions
That would be nice. Maybe by a separate change?
dp: That would be nice. Maybe by a separate change?
    int DefaultVal = IsPacked ? -1 : 0;

    addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,

                          DefaultVal);

  }
  }






  int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo);
  int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo);

  if (NegLoIdx != -1) {
  if (NegLoIdx != -1) {

    assert(IsPacked);

    addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo);
    addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo);

    addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);
    addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);

  }
  }






  const int Ops[] = { AMDGPU::OpName::src0,
  const int Ops[] = { AMDGPU::OpName::src0,

                      AMDGPU::OpName::src1,
                      AMDGPU::OpName::src1,

                      AMDGPU::OpName::src2 };
                      AMDGPU::OpName::src2 };

  const int ModOps[] = { AMDGPU::OpName::src0_modifiers,
  const int ModOps[] = { AMDGPU::OpName::src0_modifiers,

                         AMDGPU::OpName::src1_modifiers,
                         AMDGPU::OpName::src1_modifiers,

                         AMDGPU::OpName::src2_modifiers };
                         AMDGPU::OpName::src2_modifiers };




  int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
  int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);

Show All 33 Lines    if ((NegHi & (1 << J)) != 0)

      ModVal |= SISrcMods::NEG_HI;
      ModVal |= SISrcMods::NEG_HI;




    int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
    int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);




    Inst.getOperand(ModIdx).setImm(Inst.getOperand(ModIdx).getImm() | ModVal);
    Inst.getOperand(ModIdx).setImm(Inst.getOperand(ModIdx).getImm() | ModVal);

  }
  }

}
}




void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {

  cvtVOP3PImpl(Inst, Operands, true);

}



void AMDGPUAsmParser::cvtVOP3P_NotPacked(MCInst &Inst,

                                         const OperandVector &Operands) {

  cvtVOP3PImpl(Inst, Operands, false);

}



//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

// dpp
// dpp

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//




bool AMDGPUOperand::isDPPCtrl() const {
bool AMDGPUOperand::isDPPCtrl() const {

  bool result = isImm() && getImmTy() == ImmTyDppCtrl && isUInt<9>(getImm());
  bool result = isImm() && getImmTy() == ImmTyDppCtrl && isUInt<9>(getImm());

  if (result) {
  if (result) {

    int64_t Imm = getImm();
    int64_t Imm = getImm();

▲ Show 20 Lines • Show All 402 Lines • Show Last 20 Lines
lib/Target/AMDGPU/SIInstrInfo.td
Show First 20 Lines • Show All 1,630 Lines • ▼ Show 20 Lines
def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;

def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;

def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;

def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;

def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;

def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;

def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;

def VOP_V2F16_F32_F32 : VOPProfile <[v2f16, f32, f32, untyped]>;
def VOP_V2F16_F32_F32 : VOPProfile <[v2f16, f32, f32, untyped]>;

def VOP_F32_F16_F16_F16 : VOPProfile <[f32, f16, f16, f16]>;




def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;

def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;

def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;




def VOP_F16_F32_F16_F32 : VOPProfile <[f16, f32, f16, f32]>;
def VOP_F16_F32_F16_F32 : VOPProfile <[f16, f32, f16, f32]>;

def VOP_F32_F32_F16_F16 : VOPProfile <[f32, f32, f16, f16]>;
def VOP_F32_F32_F16_F16 : VOPProfile <[f32, f32, f16, f16]>;

def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;

▲ Show 20 Lines • Show All 174 Lines • Show Last 20 Lines
lib/Target/AMDGPU/VOP3PInstructions.td
Show All 14 Linesclass VOP3PInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> :

  VOP3P_Pseudo<OpName, P,
  VOP3P_Pseudo<OpName, P,

    !if(P.HasModifiers, getVOP3PModPat<P, node>.ret, getVOP3Pat<P, node>.ret)
    !if(P.HasModifiers, getVOP3PModPat<P, node>.ret, getVOP3Pat<P, node>.ret)

>;
>;




// Non-packed instructions that use the VOP3P encoding.
// Non-packed instructions that use the VOP3P encoding.

// VOP3 neg/abs and VOP3P opsel/opsel_hi modifiers are allowed.
// VOP3 neg/abs and VOP3P opsel/opsel_hi modifiers are allowed.

class VOP3_VOP3PInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> :
class VOP3_VOP3PInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> :

  VOP3P_Pseudo<OpName, P> {
  VOP3P_Pseudo<OpName, P> {

  // These operands are only sort of f16 operands. Depending on

  // op_sel_hi, these may be interpreted as f32. The inline immediate

  // values are really f16 converted to f32, so we treat these as f16

  // operands.

  let InOperandList =
  let InOperandList =

    (ins
    (ins

      FP32InputMods:$src0_modifiers, VCSrc_f32:$src0,
      FP16InputMods:$src0_modifiers, VCSrc_f16:$src0,

      FP32InputMods:$src1_modifiers, VCSrc_f32:$src1,
      FP16InputMods:$src1_modifiers, VCSrc_f16:$src1,

      FP32InputMods:$src2_modifiers, VCSrc_f32:$src2,
      FP16InputMods:$src2_modifiers, VCSrc_f16:$src2,

      clampmod:$clamp,
      clampmod:$clamp,

      op_sel:$op_sel,
      op_sel:$op_sel,

      op_sel_hi:$op_sel_hi);
      op_sel_hi:$op_sel_hi);

  let AsmOperands =
  let AsmOperands =

    " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp";
    " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp";

}
}




let isCommutable = 1 in {
let isCommutable = 1 in {

Show All 18 Lines



def V_PK_SUB_U16 : VOP3PInst<"v_pk_sub_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>>;
def V_PK_SUB_U16 : VOP3PInst<"v_pk_sub_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>>;

def V_PK_SUB_I16 : VOP3PInst<"v_pk_sub_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, sub>;
def V_PK_SUB_I16 : VOP3PInst<"v_pk_sub_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, sub>;




def V_PK_LSHLREV_B16 : VOP3PInst<"v_pk_lshlrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshl_rev>;
def V_PK_LSHLREV_B16 : VOP3PInst<"v_pk_lshlrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshl_rev>;

def V_PK_ASHRREV_I16 : VOP3PInst<"v_pk_ashrrev_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, ashr_rev>;
def V_PK_ASHRREV_I16 : VOP3PInst<"v_pk_ashrrev_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, ashr_rev>;

def V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshr_rev>;
def V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshr_rev>;




// XXX - Commutable?

// These are VOP3a-like opcodes which accept no omod.
// These are VOP3a-like opcodes which accept no omod.

// Size of src arguments (16/32) is controlled by op_sel.
// Size of src arguments (16/32) is controlled by op_sel.

// For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi.
// For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi.

def V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3_Profile<VOP_F32_V2F16_V2F16_V2F16>>;
let isCommutable = 1 in {

def V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16_V2F16>>;
def V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3_Profile<VOP_F32_F16_F16_F16>>;

def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16_V2F16>>;
def V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>;


def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>;

}




multiclass VOP3P_Real_vi<bits<10> op> {
multiclass VOP3P_Real_vi<bits<10> op> {

  def _vi : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.VI>,
  def _vi : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.VI>,

            VOP3Pe <op, !cast<VOP3P_Pseudo>(NAME).Pfl> {
            VOP3Pe <op, !cast<VOP3P_Pseudo>(NAME).Pfl> {

    let AssemblerPredicates = [HasVOP3PInsts];
    let AssemblerPredicates = [HasVOP3PInsts];

    let DecoderNamespace = "VI";
    let DecoderNamespace = "VI";

  }
  }

}
}

Show All 25 Lines
lib/Target/AMDGPU/VOPInstructions.td
Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Linesclass VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],

  let VALU = 1;
  let VALU = 1;

  let FPClamp = P.HasFPClamp;
  let FPClamp = P.HasFPClamp;

  let Uses = [EXEC];
  let Uses = [EXEC];




  let AsmVariantName = AMDGPUAsmVariants.VOP3;
  let AsmVariantName = AMDGPUAsmVariants.VOP3;

  let AsmMatchConverter =
  let AsmMatchConverter =

    !if(!and(P.IsPacked, isVOP3P),
    !if(!and(P.IsPacked, isVOP3P),

        "cvtVOP3P",
        "cvtVOP3P",

        !if(isVOP3P, "cvtVOP3P_NotPacked",

        !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
          !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),

            "cvtVOP3",
              "cvtVOP3",

            ""));
              "")));




  VOPProfile Pfl = P;
  VOPProfile Pfl = P;

}
}




class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> :
class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> :

  VOP3_Pseudo<opName, P, pattern, 1, 1> {
  VOP3_Pseudo<opName, P, pattern, 1, 1> {

  let VOP3P = 1;
  let VOP3P = 1;

}
}

▲ Show 20 Lines • Show All 397 Lines • Show Last 20 Lines
test/MC/AMDGPU/gfx9_asm_all.s
  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 99,991 Lines • ▼ Show 20 Lines



v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,0,1]
v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,0,1]

// CHECK: [0x05,0x40,0x9a,0xd2,0x01,0x05,0x02,0x00]
// CHECK: [0x05,0x40,0x9a,0xd2,0x01,0x05,0x02,0x00]




v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,1,1]
v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,1,1]

// CHECK: [0x05,0x58,0x9a,0xd2,0x01,0x05,0x02,0x00]
// CHECK: [0x05,0x58,0x9a,0xd2,0x01,0x05,0x02,0x00]




v_mad_mix_f32 v5, v1, v2, v3
v_mad_mix_f32 v5, v1, v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v255, v1, v2, v3
v_mad_mix_f32 v255, v1, v2, v3

// CHECK: [0xff,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// CHECK: [0xff,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v5, v255, v2, v3
v_mad_mix_f32 v5, v255, v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0xff,0x05,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0xff,0x05,0x0e,0x04]




v_mad_mix_f32 v5, s1, v2, v3
v_mad_mix_f32 v5, s1, v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x04,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x04,0x0e,0x04]




v_mad_mix_f32 v5, s101, v2, v3
v_mad_mix_f32 v5, s101, v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x65,0x04,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x65,0x04,0x0e,0x04]




v_mad_mix_f32 v5, flat_scratch_lo, v2, v3
v_mad_mix_f32 v5, flat_scratch_lo, v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x66,0x04,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x66,0x04,0x0e,0x04]




v_mad_mix_f32 v5, flat_scratch_hi, v2, v3
v_mad_mix_f32 v5, flat_scratch_hi, v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x67,0x04,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x67,0x04,0x0e,0x04]




v_mad_mix_f32 v5, vcc_lo, v2, v3
v_mad_mix_f32 v5, vcc_lo, v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x6a,0x04,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x6a,0x04,0x0e,0x04]




v_mad_mix_f32 v5, vcc_hi, v2, v3
v_mad_mix_f32 v5, vcc_hi, v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x6b,0x04,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x6b,0x04,0x0e,0x04]




v_mad_mix_f32 v5, m0, v2, v3
v_mad_mix_f32 v5, m0, v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x7c,0x04,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x7c,0x04,0x0e,0x04]




v_mad_mix_f32 v5, exec_lo, v2, v3
v_mad_mix_f32 v5, exec_lo, v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x7e,0x04,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x7e,0x04,0x0e,0x04]




v_mad_mix_f32 v5, exec_hi, v2, v3
v_mad_mix_f32 v5, exec_hi, v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x7f,0x04,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x7f,0x04,0x0e,0x04]




v_mad_mix_f32 v5, v1, v255, v3
v_mad_mix_f32 v5, v1, v255, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xff,0x0f,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0f,0x04]




v_mad_mix_f32 v5, v1, s2, v3
v_mad_mix_f32 v5, v1, s2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0c,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0c,0x04]




v_mad_mix_f32 v5, v1, s101, v3
v_mad_mix_f32 v5, v1, s101, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xcb,0x0c,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xcb,0x0c,0x04]




v_mad_mix_f32 v5, v1, flat_scratch_lo, v3
v_mad_mix_f32 v5, v1, flat_scratch_lo, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xcd,0x0c,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xcd,0x0c,0x04]




v_mad_mix_f32 v5, v1, flat_scratch_hi, v3
v_mad_mix_f32 v5, v1, flat_scratch_hi, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xcf,0x0c,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xcf,0x0c,0x04]




v_mad_mix_f32 v5, v1, vcc_lo, v3
v_mad_mix_f32 v5, v1, vcc_lo, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xd5,0x0c,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xd5,0x0c,0x04]




v_mad_mix_f32 v5, v1, vcc_hi, v3
v_mad_mix_f32 v5, v1, vcc_hi, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xd7,0x0c,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xd7,0x0c,0x04]




v_mad_mix_f32 v5, v1, m0, v3
v_mad_mix_f32 v5, v1, m0, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xf9,0x0c,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xf9,0x0c,0x04]




v_mad_mix_f32 v5, v1, exec_lo, v3
v_mad_mix_f32 v5, v1, exec_lo, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xfd,0x0c,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xfd,0x0c,0x04]




v_mad_mix_f32 v5, v1, exec_hi, v3
v_mad_mix_f32 v5, v1, exec_hi, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xff,0x0c,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0c,0x04]




v_mad_mix_f32 v5, v1, v2, v255
v_mad_mix_f32 v5, v1, v2, v255

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0xfe,0x1f]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x07]




v_mad_mix_f32 v5, v1, v2, s3
v_mad_mix_f32 v5, v1, v2, s3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x18]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x00]




v_mad_mix_f32 v5, v1, v2, s101
v_mad_mix_f32 v5, v1, v2, s101

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x96,0x19]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x96,0x01]




v_mad_mix_f32 v5, v1, v2, flat_scratch_lo
v_mad_mix_f32 v5, v1, v2, flat_scratch_lo

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x9a,0x19]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x9a,0x01]




v_mad_mix_f32 v5, v1, v2, flat_scratch_hi
v_mad_mix_f32 v5, v1, v2, flat_scratch_hi

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x9e,0x19]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x9e,0x01]




v_mad_mix_f32 v5, v1, v2, vcc_lo
v_mad_mix_f32 v5, v1, v2, vcc_lo

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0xaa,0x19]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xaa,0x01]




v_mad_mix_f32 v5, v1, v2, vcc_hi
v_mad_mix_f32 v5, v1, v2, vcc_hi

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0xae,0x19]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xae,0x01]




v_mad_mix_f32 v5, v1, v2, m0
v_mad_mix_f32 v5, v1, v2, m0

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0xf2,0x19]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xf2,0x01]




v_mad_mix_f32 v5, v1, v2, exec_lo
v_mad_mix_f32 v5, v1, v2, exec_lo

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0xfa,0x19]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfa,0x01]




v_mad_mix_f32 v5, v1, v2, exec_hi
v_mad_mix_f32 v5, v1, v2, exec_hi

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0xfe,0x19]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x01]




v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,0]
v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,0]

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,0,0]
v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,0,0]

// CHECK: [0x05,0x48,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,1,0]
v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,1,0]

// CHECK: [0x05,0x50,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,1]
v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,1]

// CHECK: [0x05,0x60,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,1,1]
v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,1,1]

// CHECK: [0x05,0x78,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,1,1]
v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,1,1]

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,0]
v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,0]

// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,0,0]
v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,0,0]

// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,1,0]
v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,1,0]

// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,1]
v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,1]

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04]
// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v5, -v1, v2, v3
v_mad_mix_f32 v5, -v1, v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x3c]
// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x3c]




v_mad_mix_f32 v5, v1, -v2, v3
v_mad_mix_f32 v5, v1, -v2, v3

// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x5c]
// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x5c]




v_mad_mix_f32 v5, v1, v2, -v3
v_mad_mix_f32 v5, v1, v2, -v3

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v_pk_min_f16 v0, v1, v2
v_pk_min_f16 v0, v1, v2

// GFX9: v_pk_min_f16 v0, v1, v2 ; encoding: [0x00,0x00,0x91,0xd3,0x01,0x05,0x02,0x18]
// GFX9: v_pk_min_f16 v0, v1, v2 ; encoding: [0x00,0x00,0x91,0xd3,0x01,0x05,0x02,0x18]




v_pk_max_f16 v0, v1, v2
v_pk_max_f16 v0, v1, v2

// GFX9: v_pk_max_f16 v0, v1, v2 ; encoding: [0x00,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
// GFX9: v_pk_max_f16 v0, v1, v2 ; encoding: [0x00,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]




v_mad_mix_f32 v0, v1, v2, v3
v_mad_mix_f32 v0, v1, v2, v3

// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mixlo_f16 v0, v1, v2, v3
v_mad_mixlo_f16 v0, v1, v2, v3

// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 ; encoding: [0x00,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mixhi_f16 v0, v1, v2, v3
v_mad_mixhi_f16 v0, v1, v2, v3

// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 ; encoding: [0x00,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]




//
//

// Regular source modifiers on non-packed instructions
// Regular source modifiers on non-packed instructions

//
//




v_mad_mix_f32 v0, abs(v1), v2, v3
v_mad_mix_f32 v0, abs(v1), v2, v3

// GFX9: v_mad_mix_f32 v0, |v1|, v2, v3  ; encoding: [0x00,0x41,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// GFX9: v_mad_mix_f32 v0, |v1|, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v0, v1, abs(v2), v3
v_mad_mix_f32 v0, v1, abs(v2), v3

// GFX9: v_mad_mix_f32 v0, v1, |v2|, v3  ; encoding: [0x00,0x42,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// GFX9: v_mad_mix_f32 v0, v1, |v2|, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v0, v1, v2, abs(v3)
v_mad_mix_f32 v0, v1, v2, abs(v3)

// GFX9: v_mad_mix_f32 v0, v1, v2, |v3|  ; encoding: [0x00,0x44,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// GFX9: v_mad_mix_f32 v0, v1, v2, |v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v0, -v1, v2, v3
v_mad_mix_f32 v0, -v1, v2, v3

// GFX9: v_mad_mix_f32 v0, -v1, v2, v3   ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x3c]
// GFX9: v_mad_mix_f32 v0, -v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]




v_mad_mix_f32 v0, v1, -v2, v3
v_mad_mix_f32 v0, v1, -v2, v3

// GFX9: v_mad_mix_f32 v0, v1, -v2, v3   ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x5c]
// GFX9: v_mad_mix_f32 v0, v1, -v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]




v_mad_mix_f32 v0, v1, v2, -v3
v_mad_mix_f32 v0, v1, v2, -v3

// GFX9: v_mad_mix_f32 v0, v1, v2, -v3   ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x9c]
// GFX9: v_mad_mix_f32 v0, v1, v2, -v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]




v_mad_mix_f32 v0, -abs(v1), v2, v3
v_mad_mix_f32 v0, -abs(v1), v2, v3

// GFX9: v_mad_mix_f32 v0, -|v1|, v2, v3 ; encoding: [0x00,0x41,0xa0,0xd3,0x01,0x05,0x0e,0x3c]
// GFX9: v_mad_mix_f32 v0, -|v1|, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x24]




v_mad_mix_f32 v0, v1, -abs(v2), v3
v_mad_mix_f32 v0, v1, -abs(v2), v3

// GFX9: v_mad_mix_f32 v0, v1, -|v2|, v3 ; encoding: [0x00,0x42,0xa0,0xd3,0x01,0x05,0x0e,0x5c]
// GFX9: v_mad_mix_f32 v0, v1, -|v2|, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x44]




v_mad_mix_f32 v0, v1, v2, -abs(v3)
v_mad_mix_f32 v0, v1, v2, -abs(v3)

// GFX9: v_mad_mix_f32 v0, v1, v2, -|v3| ; encoding: [0x00,0x44,0xa0,0xd3,0x01,0x05,0x0e,0x9c]
// GFX9: v_mad_mix_f32 v0, v1, v2, -|v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x84]




v_mad_mixlo_f16 v0, abs(v1), -v2, abs(v3)
v_mad_mixlo_f16 v0, abs(v1), -v2, abs(v3)

// GFX9: v_mad_mixlo_f16 v0, |v1|, -v2, |v3| ; encoding: [0x00,0x45,0xa1,0xd3,0x01,0x05,0x0e,0x5c]
// GFX9: v_mad_mixlo_f16 v0, |v1|, -v2, |v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x05,0xa1,0xd3,0x01,0x05,0x0e,0x44]




v_mad_mixhi_f16 v0, -v1, abs(v2), -abs(v3)
v_mad_mixhi_f16 v0, -v1, abs(v2), -abs(v3)

// GFX9: v_mad_mixhi_f16 v0, -v1, |v2|, -|v3| ; encoding: [0x00,0x46,0xa2,0xd3,0x01,0x05,0x0e,0xbc]
// GFX9: v_mad_mixhi_f16 v0, -v1, |v2|, -|v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x06,0xa2,0xd3,0x01,0x05,0x0e,0xa4]



v_mad_mixlo_f16 v0, v1, v2, v3 clamp

// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] clamp ; encoding: [0x00,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]



v_mad_mixhi_f16 v0, v1, v2, v3 clamp

// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] clamp ; encoding: [0x00,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]




//
//

// op_sel with non-packed instructions
// op_sel with non-packed instructions

//
//




v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,0]
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,0]

// GFX9: v_mad_mix_f32 v0, v1, v2, v3    ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0]
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0]

// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x00,0x48,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0]
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0]

// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x00,0x50,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1]
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1]

// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x00,0x60,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1] op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1]
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1]

// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x00,0x78,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1] op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0]
v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0]

// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,0,0]
v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,0,0]

// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c]
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,1,0]
v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,1,0]

// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14]
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,1]
v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,1]

// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,1] ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04]
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,1] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]




v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,1,1]
v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,1,1]

// GFX9: v_mad_mix_f32 v0, v1, v2, v3    ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
// GFX9: v_mad_mix_f32 v0, v1, v2, v3    ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]



v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp

// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp ; encoding: [0x00,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]



v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp

// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp ; encoding: [0x00,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]