[MIPS] Add support to match more patterns for BBIT instruction.

[spetrovic]

Summary

This patch supports one more pattern for bbit0 and bbit1 instructions, I expanded CBranchBitNum class so it can take 32 bit immidate. Example:

long long var = 7;
void bbit0i32 () {

if ((var & 0x2)) {
  printf("bbit0i32");
}

}

Before the patch:

0000000000000000 <bbit0i32>:

 0:	67bdfff0 	daddiu	sp,sp,-16
 4:	ffbf0008 	sd	ra,8(sp)
 8:	ffbc0000 	sd	gp,0(sp)
 c:	3c010000 	lui	at,0x0
10:	0039082d 	daddu	at,at,t9
14:	643c0000 	daddiu	gp,at,0
18:	3c010000 	lui	at,0x0
1c:	003c082d 	daddu	at,at,gp
20:	dc210000 	ld	at,0(at)
24:	90210007 	lbu	at,7(at)
28:	30210002 	andi	at,at,0x2
2c:	10200008 	beqz	at,50 <bbit0i32+0x50>
30:	00000000 	nop
34:	df810000 	ld	at,0(gp)
38:	64240000 	daddiu	a0,at,0
3c:	3c010000 	lui	at,0x0
40:	003c082d 	daddu	at,at,gp
44:	dc390000 	ld	t9,0(at)
48:	0320f809 	jalr	t9
4c:	00000000 	nop
50:	dfbc0000 	ld	gp,0(sp)
54:	dfbf0008 	ld	ra,8(sp)
58:	03e00008 	jr	ra
5c:	67bd0010 	daddiu	sp,sp,16

With the patch:

0000000000000000 <bbit0i32>:

 0:	67bdfff0 	daddiu	sp,sp,-16
 4:	ffbf0008 	sd	ra,8(sp)
 8:	ffbc0000 	sd	gp,0(sp)
 c:	3c010000 	lui	at,0x0
10:	0039082d 	daddu	at,at,t9
14:	643c0000 	daddiu	gp,at,0
18:	3c010000 	lui	at,0x0
1c:	003c082d 	daddu	at,at,gp
20:	dc210000 	ld	at,0(at)
24:	90210007 	lbu	at,7(at)
28:	c8210008 	bbit0	at,0x1,4c <bbit0i32+0x4c>
2c:	00000000 	nop
30:	df810000 	ld	at,0(gp)
34:	64240000 	daddiu	a0,at,0
38:	3c010000 	lui	at,0x0
3c:	003c082d 	daddu	at,at,gp
40:	dc390000 	ld	t9,0(at)
44:	0320f809 	jalr	t9
48:	00000000 	nop
4c:	dfbc0000 	ld	gp,0(sp)
50:	dfbf0008 	ld	ra,8(sp)
54:	03e00008 	jr	ra
58:	67bd0010 	daddiu	sp,sp,16

[sdardis]

Don't forget to add llvm-commits when posting.

[sdardis]

The approach here is somewhat overly verbose and can be dramatically simplified:

def : MipsPat<(brcond (i32 (seteq (and i32:$lhs, PowerOf2LO_i32:$mask), 0)),
                       bb:$dst),
              (BBIT0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32),
                     (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;

achieves the same result without having to define new instructions and the relevant branch analysis. Can you use that approach rather than defining codegen only instructions?

[sdardis]

Also, can you simplify the test cases to call some external function such as "void g(void)" ?

[spetrovic]

Comments addressed.

[sdardis]

LGTM with inline nits addressed.

lib/Target/Mips/Mips64InstrInfo.td

64

Use isUInt<32>(Imm) here.

test/CodeGen/Mips/octeon.ll

186

This needs ALL-LABEL: bbit0i32:

204

This needs ALL-LABEL: bbit0i32:

[spetrovic]

Comments addressed.

lib/Target/Mips/Mips64InstrInfo.td

def PowerOf2HI : PatLeaf<(imm), [{
   if (N->getValueType(0) == MVT::i64) {
     uint64_t Imm = N->getZExtValue();
     return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm;
   }
   else
     return false;
 }]>;
 
+def PowerOf2LO_i32 : PatLeaf<(imm), [{
+  if (N->getValueType(0) == MVT::i32) {
+    uint64_t Imm = N->getZExtValue();
+    return isPowerOf2_32(Imm) && (Imm & 0xffffffff) == Imm;
+  }
+  else
+    return false;
+}]>;
+
 def assertzext_lt_i32 : PatFrag<(ops node:$src), (assertzext node:$src), [{
   return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32);
 }]>;
 
 //===----------------------------------------------------------------------===//
 // Instructions specific format
 //===----------------------------------------------------------------------===//
 let usesCustomInserter = 1 in {
InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
          !strconcat(opstr, "\t$rt, $rs, $imm10"),
          [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
                                              immSExt10_64:$imm10)))],
          II_SEQI_SNEI, FrmI, opstr> {
   let TwoOperandAliasConstraint = "$rt = $rs";
 }
 
 class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
-                    RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> :
+                    RegisterOperand RO, PatFrag ImmShift, Operand ImmOp,
+                    bits<64> shift = 1> :
   InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),
          !strconcat(opstr, "\t$rs, $p, $offset"),
-         [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
+         [(brcond (i32 (cond_op (and RO:$rs, (shl shift, ImmShift:$p)), 0)),
                   bb:$offset)], II_BBIT, FrmI, opstr> {
   let isBranch = 1;
   let isTerminator = 1;
   let hasDelaySlot = 1;
   let Defs = [AT];
 }
 
 class MFC2OP<string asmstr, RegisterOperand RO, InstrItinClass itin> :
   InstSE<(outs RO:$rt, uimm16:$imm16), (ins),
          !strconcat(asmstr, "\t$rt, $imm16"), [], itin, FrmFR>;
 
 // Unsigned Byte Add
 def BADDu  : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
              ADD_FM<0x1c, 0x28>, ASE_CNMIPS {
   let Pattern = [(set GPR64Opnd:$rd,
                       (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))];
 }
 
 // Branch on Bit Clear /+32
-def BBIT0  : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd,
+def BBIT0  : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd, immZExt5_64,
                            uimm5_64_report_uimm6>, BBIT_FM<0x32>, ASE_CNMIPS;
-def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64,
-                           0x100000000>, BBIT_FM<0x36>, ASE_CNMIPS;
+def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, immZExt5_64,
+                           uimm5_64, 0x100000000>, BBIT_FM<0x36>, ASE_CNMIPS;
 
 // Branch on Bit Set /+32
-def BBIT1  : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd,
+def BBIT1  : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd, immZExt5_64,
                            uimm5_64_report_uimm6>, BBIT_FM<0x3a>, ASE_CNMIPS;
-def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64,
-                           0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS;
+def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, immZExt5_64,
+                           uimm5_64, 0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS;
+
+let isCodeGenOnly = 1 in
+  def BBIT0_i32  : CBranchBitNum<"bbit0", brtarget, seteq, GPR32Opnd, immZExt5,
+                           uimm5_report_uimm6>, BBIT_FM<0x32>, ASE_CNMIPS;
+let isCodeGenOnly = 1 in
+  def BBIT1_i32  : CBranchBitNum<"bbit1", brtarget, setne, GPR32Opnd, immZExt5,
+                           uimm5_report_uimm6>, BBIT_FM<0x3a>, ASE_CNMIPS;
 
 // Multiply Doubleword to GPR
 def DMUL  : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
             ADD_FM<0x1c, 0x03>, ASE_CNMIPS {
   let Defs = [HI0, LO0, P0, P1, P2];
 }
 
 let AdditionalPredicates = [NotInMicroMips] in {

 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
               (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
               (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
               (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
               (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
+def : MipsPat<(brcond (i32 (seteq (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst),
+              (BBIT0_i32 i32:$lhs, (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
+def : MipsPat<(brcond (i32 (setne (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst),
+              (BBIT1_i32 i32:$lhs, (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
 
 // Atomic load patterns.
 def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>;
 def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>;
 def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>;
 def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>;
 
 // Atomic store patterns.

lib/Target/Mips/MipsSEInstrInfo.cpp

unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
   case Mips::BGTZC64:  return Mips::BLEZC64;
   case Mips::BGEZC64:  return Mips::BLTZC64;
   case Mips::BLTZC64:  return Mips::BGEZC64;
   case Mips::BLEZC64:  return Mips::BGTZC64;
   case Mips::BBIT0:  return Mips::BBIT1;
   case Mips::BBIT1:  return Mips::BBIT0;
   case Mips::BBIT032:  return Mips::BBIT132;
   case Mips::BBIT132:  return Mips::BBIT032;
+  case Mips::BBIT0_i32:  return Mips::BBIT1_i32;
+  case Mips::BBIT1_i32:  return Mips::BBIT0_i32;
   }
 }
 
 /// Adjust SP by Amount bytes.
 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
                                      MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I) const {
   MipsABIInfo ABI = Subtarget.getABI();
return (Opc == Mips::BEQ    || Opc == Mips::BEQ_MM || Opc == Mips::BNE    ||
           Opc == Mips::BLEZC  || Opc == Mips::BGEZC  || Opc == Mips::BLTZC  ||
           Opc == Mips::BEQZC  || Opc == Mips::BNEZC  || Opc == Mips::BEQZC64 ||
           Opc == Mips::BNEZC64 || Opc == Mips::BEQC64 || Opc == Mips::BNEC64 ||
           Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 ||
           Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 ||
           Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 ||
           Opc == Mips::BLEZC64 || Opc == Mips::BC || Opc == Mips::BBIT0 ||
           Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
-          Opc == Mips::BBIT132) ? Opc : 0;
+          Opc == Mips::BBIT132 || Opc == Mips::BBIT0_i32 ||
+          Opc == Mips::BBIT1_i32) ? Opc : 0;
 }
 
 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I) const {
 
   MachineInstrBuilder MIB;
   if (Subtarget.isGP64bit())
     MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))

test/CodeGen/Mips/octeon.ll

; MIPS64: beqz    $[[T2]], [[BB0:(\$|\.L)BB[0-9_]+]]
   %res = icmp ne i64 %bit, 0
   br i1 %res, label %endif, label %if
 if:
   ret i64 48
 
 endif:
   ret i64 12
 }
+
+; long long var = 7;
+; void bbit0i32 () {
+;   if ((var & 0x2)) {
+;     printf("bbit0i32");
+;   }
+; }
+;
+; void bbit1i32() {
+;   if (!(var & 0x2)) {
+;     printf("bbit1i32");
+;   }
+; }
+
+@var = local_unnamed_addr global i64 7, align 8
+@.str = private unnamed_addr constant [9 x i8] c"bbit0i32\00", align 1
+@.str.1 = private unnamed_addr constant [9 x i8] c"bbit1i32\00", align 1
+
+define void @bbit0i32() local_unnamed_addr {
+entry:
+; OCTEON: bbit0 $1, 1, [[BB0:(\$|\.L)BB[0-9_]+]]
+; OCTEON-PIC-NOT: b  {{[[:space:]].*}}
+; OCTEON-NOT: j  {{[[:space:]].*}}
+  %0 = load i64, i64* @var, align 8
+  %and = and i64 %0, 2
+  %tobool = icmp eq i64 %and, 0
+  br i1 %tobool, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i64 0, i64 0))
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+  ret void
+}
+
+declare i32 @printf(i8* nocapture readonly, ...) local_unnamed_addr
+
+define void @bbit1i32() local_unnamed_addr {
+entry:
+; OCTEON: bbit1 $1, 1, [[BB0:(\$|\.L)BB[0-9_]+]]
+; OCTEON-PIC-NOT: b  {{[[:space:]].*}}
+; OCTEON-NOT: j  {{[[:space:]].*}}
+  %0 = load i64, i64* @var, align 8
+  %and = and i64 %0, 2
+  %tobool = icmp eq i64 %and, 0
+  br i1 %tobool, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i64 0, i64 0))
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+  ret void
+}
+