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[MIPS] Add support to match more patterns for BBIT instruction.
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Authored by spetrovic on Aug 2 2017, 7:54 AM.

Details

Summary

This patch supports one more pattern for bbit0 and bbit1 instructions, I expanded CBranchBitNum class so it can take 32 bit immidate. Example:

long long var = 7;
void bbit0i32 () {

if ((var & 0x2)) {
  printf("bbit0i32");
}

}

Before the patch:

0000000000000000 <bbit0i32>:

 0:	67bdfff0 	daddiu	sp,sp,-16
 4:	ffbf0008 	sd	ra,8(sp)
 8:	ffbc0000 	sd	gp,0(sp)
 c:	3c010000 	lui	at,0x0
10:	0039082d 	daddu	at,at,t9
14:	643c0000 	daddiu	gp,at,0
18:	3c010000 	lui	at,0x0
1c:	003c082d 	daddu	at,at,gp
20:	dc210000 	ld	at,0(at)
24:	90210007 	lbu	at,7(at)
28:	30210002 	andi	at,at,0x2
2c:	10200008 	beqz	at,50 <bbit0i32+0x50>
30:	00000000 	nop
34:	df810000 	ld	at,0(gp)
38:	64240000 	daddiu	a0,at,0
3c:	3c010000 	lui	at,0x0
40:	003c082d 	daddu	at,at,gp
44:	dc390000 	ld	t9,0(at)
48:	0320f809 	jalr	t9
4c:	00000000 	nop
50:	dfbc0000 	ld	gp,0(sp)
54:	dfbf0008 	ld	ra,8(sp)
58:	03e00008 	jr	ra
5c:	67bd0010 	daddiu	sp,sp,16

With the patch:

0000000000000000 <bbit0i32>:

 0:	67bdfff0 	daddiu	sp,sp,-16
 4:	ffbf0008 	sd	ra,8(sp)
 8:	ffbc0000 	sd	gp,0(sp)
 c:	3c010000 	lui	at,0x0
10:	0039082d 	daddu	at,at,t9
14:	643c0000 	daddiu	gp,at,0
18:	3c010000 	lui	at,0x0
1c:	003c082d 	daddu	at,at,gp
20:	dc210000 	ld	at,0(at)
24:	90210007 	lbu	at,7(at)
28:	c8210008 	bbit0	at,0x1,4c <bbit0i32+0x4c>
2c:	00000000 	nop
30:	df810000 	ld	at,0(gp)
34:	64240000 	daddiu	a0,at,0
38:	3c010000 	lui	at,0x0
3c:	003c082d 	daddu	at,at,gp
40:	dc390000 	ld	t9,0(at)
44:	0320f809 	jalr	t9
48:	00000000 	nop
4c:	dfbc0000 	ld	gp,0(sp)
50:	dfbf0008 	ld	ra,8(sp)
54:	03e00008 	jr	ra
58:	67bd0010 	daddiu	sp,sp,16

Diff Detail

Repository
rL LLVM

Event Timeline

spetrovic created this revision.Aug 2 2017, 7:54 AM
spetrovic updated this revision to Diff 109353.Aug 2 2017, 7:56 AM
spetrovic retitled this revision from [MIPS] Add support to match more patterns for DINS instruction. to [MIPS] Add support to match more patterns for BBIT instruction..
sdardis edited edge metadata.Aug 2 2017, 8:11 AM
sdardis added a subscriber: llvm-commits.

Don't forget to add llvm-commits when posting.

The approach here is somewhat overly verbose and can be dramatically simplified:

def : MipsPat<(brcond (i32 (seteq (and i32:$lhs, PowerOf2LO_i32:$mask), 0)),
                       bb:$dst),
              (BBIT0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32),
                     (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;

achieves the same result without having to define new instructions and the relevant branch analysis. Can you use that approach rather than defining codegen only instructions?

Also, can you simplify the test cases to call some external function such as "void g(void)" ?

spetrovic updated this revision to Diff 109726.Aug 4 2017, 7:07 AM

Comments addressed.

sdardis accepted this revision.Aug 10 2017, 9:04 AM

LGTM with inline nits addressed.

lib/Target/Mips/Mips64InstrInfo.td
64 ↗(On Diff #109726)

Use isUInt<32>(Imm) here.

test/CodeGen/Mips/octeon.ll
186 ↗(On Diff #109726)

This needs ALL-LABEL: bbit0i32:

204 ↗(On Diff #109726)

This needs ALL-LABEL: bbit0i32:

This revision is now accepted and ready to land.Aug 10 2017, 9:04 AM
spetrovic updated this revision to Diff 112887.Aug 28 2017, 6:14 AM

Comments addressed.

This revision was automatically updated to reflect the committed changes.