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Differential D36218

AMDGPU/GlobalISel: Mark 32-bit G_FMUL as legal
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Authored by tstellar on Aug 2 2017, 6:44 AM.

Details

Reviewers
arsenm
Commits
rG3337d743999a: AMDGPU/GlobalISel: Mark 32-bit G_FMUL as legal
rL309898: AMDGPU/GlobalISel: Mark 32-bit G_FMUL as legal

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Repository
rL LLVM

Event Timeline

tstellar created this revision.Aug 2 2017, 6:44 AM
Herald added subscribers: t-tye, tpr, dstuttard and 7 others. · View Herald TranscriptAug 2 2017, 6:44 AM
arsenm accepted this revision.Aug 2 2017, 8:19 AM

LGTM

This revision is now accepted and ready to land.Aug 2 2017, 8:19 AM
Closed by commit rL309898: AMDGPU/GlobalISel: Mark 32-bit G_FMUL as legal (authored by tstellar). · Explain WhyAug 2 2017, 3:57 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
22 lines

Diff 109448

llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo() {
// values may not be legal. We need to figure out how to distinguish // values may not be legal. We need to figure out how to distinguish
// between these two scenarios. // between these two scenarios.
setAction({G_CONSTANT, S1}, Legal); setAction({G_CONSTANT, S1}, Legal);
setAction({G_CONSTANT, S32}, Legal); setAction({G_CONSTANT, S32}, Legal);
setAction({G_CONSTANT, S64}, Legal); setAction({G_CONSTANT, S64}, Legal);
setAction({G_FCONSTANT, S32}, Legal); setAction({G_FCONSTANT, S32}, Legal);
setAction({G_FMUL, S32}, Legal);
setAction({G_GEP, P1}, Legal); setAction({G_GEP, P1}, Legal);
setAction({G_GEP, P2}, Legal); setAction({G_GEP, P2}, Legal);
setAction({G_GEP, 1, S64}, Legal); setAction({G_GEP, 1, S64}, Legal);
setAction({G_ICMP, S1}, Legal); setAction({G_ICMP, S1}, Legal);
setAction({G_ICMP, 1, S32}, Legal); setAction({G_ICMP, 1, S32}, Legal);
setAction({G_LOAD, P1}, Legal); setAction({G_LOAD, P1}, Legal);
Show All 27 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir

# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
define void @test_fmul() { ret void }
...
---
name: test_fmul
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: %vgpr0, %vgpr1
; CHECK-LABEL: name: test_fmul
; CHECK: %2(s32) = G_FMUL %0, %1
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_FMUL %0, %1
...