AMDGPU/R600: Initialize more passes

[arsenm]

LGTM

llvm/trunk/lib/Target/AMDGPU/AMDGPU.h

 
 ModulePass *createAMDGPULowerIntrinsicsPass();
 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
 extern char &AMDGPULowerIntrinsicsID;
 
 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
 extern char &AMDGPURewriteOutArgumentsID;
 
+void initializeR600ClauseMergePassPass(PassRegistry &);
+extern char &R600ClauseMergePassID;
+
+void initializeR600ControlFlowFinalizerPass(PassRegistry &);
+extern char &R600ControlFlowFinalizerID;
+
+void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
+extern char &R600ExpandSpecialInstrsPassID;
+
+void initializeR600VectorRegMergerPass(PassRegistry &);
+extern char &R600VectorRegMergerID;
+
+void initializeR600PacketizerPass(PassRegistry &);
+extern char &R600PacketizerID;
+
 void initializeSIFoldOperandsPass(PassRegistry &);
 extern char &SIFoldOperandsID;
 
 void initializeSIPeepholeSDWAPass(PassRegistry &);
 extern char &SIPeepholeSDWAID;
 
 void initializeSIShrinkInstructionsPass(PassRegistry&);
 extern char &SIShrinkInstructionsID;

llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

static cl::opt<bool> EnableAMDGPUFunctionCalls(
   cl::init(false));
 
 extern "C" void LLVMInitializeAMDGPUTarget() {
   // Register the target
   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
 
   PassRegistry *PR = PassRegistry::getPassRegistry();
+  initializeR600ClauseMergePassPass(*PR);
+  initializeR600ControlFlowFinalizerPass(*PR);
+  initializeR600PacketizerPass(*PR);
+  initializeR600ExpandSpecialInstrsPassPass(*PR);
+  initializeR600VectorRegMergerPass(*PR);
   initializeSILowerI1CopiesPass(*PR);
   initializeSIFixSGPRCopiesPass(*PR);
   initializeSIFixVGPRCopiesPass(*PR);
   initializeSIFoldOperandsPass(*PR);
   initializeSIPeepholeSDWAPass(*PR);
   initializeSIShrinkInstructionsPass(*PR);
   initializeSIFixControlFlowLiveIntervalsPass(*PR);
   initializeSIOptimizeExecMaskingPreRAPass(*PR);

llvm/trunk/lib/Target/AMDGPU/R600ClauseMergePass.cpp

static bool isCFAlu(const MachineInstr &MI) {
   default:
     return false;
   }
 }
 
 class R600ClauseMergePass : public MachineFunctionPass {
 
 private:
-  static char ID;
   const R600InstrInfo *TII;
 
   unsigned getCFAluSize(const MachineInstr &MI) const;
   bool isCFAluEnabled(const MachineInstr &MI) const;
 
   /// IfCvt pass can generate "disabled" ALU clause marker that need to be
   /// removed and their content affected to the previous alu clause.
   /// This function parse instructions after CFAlu until it find a disabled
   /// CFAlu and merge the content, or an enabled CFAlu.
   void cleanPotentialDisabledCFAlu(MachineInstr &CFAlu) const;
 
   /// Check whether LatrCFAlu can be merged into RootCFAlu and do it if
   /// it is the case.
   bool mergeIfPossible(MachineInstr &RootCFAlu,
                        const MachineInstr &LatrCFAlu) const;
 
 public:
+  static char ID;
+
   R600ClauseMergePass() : MachineFunctionPass(ID) { }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   StringRef getPassName() const override;
 };
 
+} // end anonymous namespace
+
+INITIALIZE_PASS_BEGIN(R600ClauseMergePass, DEBUG_TYPE,
+                      "R600 Clause Merge", false, false)
+INITIALIZE_PASS_END(R600ClauseMergePass, DEBUG_TYPE,
+                    "R600 Clause Merge", false, false)
+
 char R600ClauseMergePass::ID = 0;
 
+char &llvm::R600ClauseMergePassID = R600ClauseMergePass::ID;
+
 unsigned R600ClauseMergePass::getCFAluSize(const MachineInstr &MI) const {
   assert(isCFAlu(MI));
   return MI
       .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::COUNT))
       .getImm();
 }
 
 bool R600ClauseMergePass::isCFAluEnabled(const MachineInstr &MI) const {
bool R600ClauseMergePass::runOnMachineFunction(MachineFunction &MF) {
   }
   return false;
 }
 
 StringRef R600ClauseMergePass::getPassName() const {
   return "R600 Merge Clause Markers Pass";
 }
 
-} // end anonymous namespace
-
-
 llvm::FunctionPass *llvm::createR600ClauseMergePass() {
   return new R600ClauseMergePass();
 }

llvm/trunk/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp

enum ControlFlowInstruction {
     CF_LOOP_BREAK,
     CF_LOOP_CONTINUE,
     CF_JUMP,
     CF_ELSE,
     CF_POP,
     CF_END
   };
 
-  static char ID;
   const R600InstrInfo *TII = nullptr;
   const R600RegisterInfo *TRI = nullptr;
   unsigned MaxFetchInst;
   const R600Subtarget *ST = nullptr;
 
   bool IsTrivialInst(MachineInstr &MI) const {
     switch (MI.getOpcode()) {
     case AMDGPU::KILL:
private:
   void CounterPropagateAddr(const std::set<MachineInstr *> &MIs,
                             unsigned Addr) const {
     for (MachineInstr *MI : MIs) {
       CounterPropagateAddr(*MI, Addr);
     }
   }
 
 public:
+  static char ID;
+
   R600ControlFlowFinalizer() : MachineFunctionPass(ID) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     ST = &MF.getSubtarget<R600Subtarget>();
     MaxFetchInst = ST->getTexVTXClauseSize();
     TII = ST->getInstrInfo();
     TRI = ST->getRegisterInfo();
 
bool runOnMachineFunction(MachineFunction &MF) override {
     return false;
   }
 
   StringRef getPassName() const override {
     return "R600 Control Flow Finalizer Pass";
   }
 };
 
+} // end anonymous namespace
+
+INITIALIZE_PASS_BEGIN(R600ControlFlowFinalizer, DEBUG_TYPE,
+                     "R600 Control Flow Finalizer", false, false)
+INITIALIZE_PASS_END(R600ControlFlowFinalizer, DEBUG_TYPE,
+                    "R600 Control Flow Finalizer", false, false)
+
 char R600ControlFlowFinalizer::ID = 0;
 
-} // end anonymous namespace
+char &llvm::R600ControlFlowFinalizerID = R600ControlFlowFinalizer::ID;
 
 FunctionPass *llvm::createR600ControlFlowFinalizer() {
   return new R600ControlFlowFinalizer();
 }

llvm/trunk/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp

 #include "R600MachineFunctionInfo.h"
 #include "R600RegisterInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 
 using namespace llvm;
 
+#define DEBUG_TYPE "r600-expand-special-instrs"
+
 namespace {
 
 class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
 private:
-  static char ID;
   const R600InstrInfo *TII;
 
   void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI,
       unsigned Op);
 
 public:
+  static char ID;
+
   R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID),
     TII(nullptr) { }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   StringRef getPassName() const override {
     return "R600 Expand special instructions pass";
   }
 };
 
 } // End anonymous namespace
 
+INITIALIZE_PASS_BEGIN(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
+                     "R600 Expand Special Instrs", false, false)
+INITIALIZE_PASS_END(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
+                    "R600ExpandSpecialInstrs", false, false)
+
 char R600ExpandSpecialInstrsPass::ID = 0;
 
+char &llvm::R600ExpandSpecialInstrsPassID = R600ExpandSpecialInstrsPass::ID;
+
 FunctionPass *llvm::createR600ExpandSpecialInstrsPass() {
   return new R600ExpandSpecialInstrsPass();
 }
 
 void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
     const MachineInstr *OldMI, unsigned Op) {
   int OpIdx = TII->getOperandIdx(*OldMI, Op);
   if (OpIdx > -1) {

llvm/trunk/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

StringRef getPassName() const override {
     return "R600 Vector Registers Merge Pass";
   }
 
   bool runOnMachineFunction(MachineFunction &Fn) override;
 };
 
 } // end anonymous namespace.
 
+INITIALIZE_PASS_BEGIN(R600VectorRegMerger, DEBUG_TYPE,
+                     "R600 Vector Reg Merger", false, false)
+INITIALIZE_PASS_END(R600VectorRegMerger, DEBUG_TYPE,
+                    "R600 Vector Reg Merger", false, false)
+
 char R600VectorRegMerger::ID = 0;
 
+char &llvm::R600VectorRegMergerID = R600VectorRegMerger::ID;
+
 bool R600VectorRegMerger::canSwizzle(const MachineInstr &MI)
     const {
   if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
     return true;
   switch (MI.getOpcode()) {
   case AMDGPU::R600_ExportSwz:
   case AMDGPU::EG_ExportSwz:
     return true;

llvm/trunk/lib/Target/AMDGPU/R600Packetizer.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addPreserved<MachineLoopInfo>();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   StringRef getPassName() const override { return "R600 Packetizer"; }
 
   bool runOnMachineFunction(MachineFunction &Fn) override;
 };
-char R600Packetizer::ID = 0;
 
 class R600PacketizerList : public VLIWPacketizerList {
 private:
   const R600InstrInfo *TII;
   const R600RegisterInfo &TRI;
   bool VLIW5;
   bool ConsideredInstUsesAlreadyWrittenVectorElement;
 
bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
   }
 
   return true;
 
 }
 
 } // end anonymous namespace
 
+INITIALIZE_PASS_BEGIN(R600Packetizer, DEBUG_TYPE,
+                     "R600 Packetizer", false, false)
+INITIALIZE_PASS_END(R600Packetizer, DEBUG_TYPE,
+                    "R600 Packetizer", false, false)
+
+char R600Packetizer::ID = 0;
+
+char &llvm::R600PacketizerID = R600Packetizer::ID;
+
 llvm::FunctionPass *llvm::createR600Packetizer() {
   return new R600Packetizer();
 }