Guard print() functions only used by dump() functions.

[fhahn]

Summary

Since r293359, most dump() function are only defined when
!defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) holds. print() functions
only used by dump() functions are now unused in release builds,
generating lots of warnings. This patch only defines some print()
functions if they are used.

[fhahn]

This patch also adds guards for a few functions not used by dump(), but only inside DEBUG(). I could split them off if that's preferred.

[MatzeB]

So I guess those print() functions are not publicly accessible (I guess we wouldn't warn about them otherwise). If the print functions aren't used otherwise, then why not merge them into the dump() functions?

[MatzeB]

In D35949#822975, @MatzeB wrote:

So I guess those print() functions are not publicly accessible (I guess we wouldn't warn about them otherwise). If the print functions aren't used otherwise, then why not merge them into the dump() functions?

Ah that makes sense. Go ahead then for those cases.

[fhahn]

I think it shouldn't be to hard to fold the print() functions into the dump() functions in most cases. I could update the patch. The only benefit of having those print functions would be debugging, in the rare case someone wants to print to a different stream then stderr.

[fhahn]

Thanks for having a look. Committed as is because some print functions are used in implementations of
raw_ostream &operator<<(raw_ostream &OS, const X &X), which in turn are used in DEBUG()

[hintonda]

lib/CodeGen/LiveDebugVariables.cpp

354

Since this is only called when NDEBUG is not defined, #ifndef NDEBUG should be moved here to fix buildbot failures.

[fhahn]

lib/CodeGen/LiveDebugVariables.cpp

354

I'll fix that, thanks

lib/CodeGen/CodeGenPrepare.cpp

 
 #ifndef NDEBUG
 static inline raw_ostream &operator<<(raw_ostream &OS, const ExtAddrMode &AM) {
   AM.print(OS);
   return OS;
 }
 #endif
 
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 void ExtAddrMode::print(raw_ostream &OS) const {
   bool NeedPlus = false;
   OS << "[";
   if (BaseGV) {
     OS << (NeedPlus ? " + " : "")
        << "GV:";
     BaseGV->printAsOperand(OS, /*PrintType=*/false);
     NeedPlus = true;
if (Scale) {
     OS << (NeedPlus ? " + " : "")
        << Scale << "*";
     ScaledReg->printAsOperand(OS, /*PrintType=*/false);
   }
 
   OS << ']';
 }
 
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD void ExtAddrMode::dump() const {
   print(dbgs());
   dbgs() << '\n';
 }
 #endif
 
 /// \brief This class provides transaction based operation on the IR.
 /// Every change made through this class is recorded in the internal state and

lib/CodeGen/LiveDebugVariables.cpp

static void printDebugLoc(const DebugLoc &DL, raw_ostream &CommentOS,
   if (!InlinedAtDL)
     return;
 
   CommentOS << " @[ ";
   printDebugLoc(InlinedAtDL, CommentOS, Ctx);
   CommentOS << " ]";
 }
 
 static void printExtendedName(raw_ostream &OS, const DILocalVariable *V,
                               const DILocation *DL) {
   const LLVMContext &Ctx = V->getContext();
   StringRef Res = V->getName();
   if (!Res.empty())
     OS << Res << "," << V->getLine();
   if (auto *InlinedAt = DL->getInlinedAt()) {
     if (DebugLoc InlinedAtDL = InlinedAt) {
       OS << " @[";
       printDebugLoc(InlinedAtDL, OS, Ctx);
       OS << "]";
     }
   }
 }
 
+#ifndef NDEBUG
 void UserValue::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
   auto *DV = cast<DILocalVariable>(Variable);
   OS << "!\"";
   printExtendedName(OS, DV, dl);
 
   OS << "\"\t";
   if (offset)
     OS << '+' << offset;
void UserValue::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
   OS << '\n';
 }
 
 void LDVImpl::print(raw_ostream &OS) {
   OS << "********** DEBUG VARIABLES **********\n";
   for (unsigned i = 0, e = userValues.size(); i != e; ++i)
     userValues[i]->print(OS, TRI);
 }
+#endif
 
 void UserValue::coalesceLocation(unsigned LocNo) {
   unsigned KeepLoc = 0;
   for (unsigned e = locations.size(); KeepLoc != e; ++KeepLoc) {
     if (KeepLoc == LocNo)
       continue;
     if (locations[KeepLoc].isIdenticalTo(locations[LocNo]))
       break;

lib/CodeGen/MachinePipeliner.cpp

for (int Cycle = getFirstCycle(), E = getFinalCycle(); Cycle <= E; ++Cycle) {
     // Replace the old order with the new order.
     cycleInstrs.swap(newOrderZC);
     cycleInstrs.insert(cycleInstrs.end(), newOrderI.begin(), newOrderI.end());
   }
 
   DEBUG(dump(););
 }
 
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 /// Print the schedule information to the given output.
 void SMSchedule::print(raw_ostream &os) const {
   // Iterate over each cycle.
   for (int cycle = getFirstCycle(); cycle <= getFinalCycle(); ++cycle) {
     // Iterate over each instruction in the cycle.
     const_sched_iterator cycleInstrs = ScheduledInstrs.find(cycle);
     for (SUnit *CI : cycleInstrs->second) {
       os << "cycle " << cycle << " (" << stageScheduled(CI) << ") ";
       os << "(" << CI->NodeNum << ") ";
       CI->getInstr()->print(os);
       os << "\n";
     }
   }
 }
 
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 /// Utility function used for debugging to print the schedule.
 LLVM_DUMP_METHOD void SMSchedule::dump() const { print(dbgs()); }
 #endif

lib/CodeGen/WinEHPrepare.cpp

for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE;) {
     MergeBlockIntoPredecessor(BB);
   }
 
   // We might have some unreachable blocks after cleaning up some impossible
   // control flow.
   removeUnreachableBlocks(F);
 }
 
+#ifndef NDEBUG
 void WinEHPrepare::verifyPreparedFunclets(Function &F) {
   for (BasicBlock &BB : F) {
     size_t NumColors = BlockColors[&BB].size();
     assert(NumColors == 1 && "Expected monochromatic BB!");
     if (NumColors == 0)
       report_fatal_error("Uncolored BB!");
     if (NumColors > 1)
       report_fatal_error("Multicolor BB!");
     assert((DisableDemotion || !(BB.isEHPad() && isa<PHINode>(BB.begin()))) &&
            "EH Pad still has a PHI!");
   }
 }
+#endif
 
 bool WinEHPrepare::prepareExplicitEH(Function &F) {
   // Remove unreachable blocks.  It is not valuable to assign them a color and
   // their existence can trick us into thinking values are alive when they are
   // not.
   removeUnreachableBlocks(F);
 
   // Determine which blocks are reachable from which funclet entries.

lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

bool PHILinearize::isSource(unsigned Reg, MachineBasicBlock *SourceMBB) {
   unsigned DestReg;
   return findDest(Reg, SourceMBB, DestReg);
 }
 
 unsigned PHILinearize::getNumSources(unsigned DestReg) {
   return phiInfoElementGetSources(findPHIInfoElement(DestReg)).size();
 }
 
-void PHILinearize::dump(MachineRegisterInfo *MRI) {
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
+LLVM_DUMP_METHOD void PHILinearize::dump(MachineRegisterInfo *MRI) {
   const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
   dbgs() << "=PHIInfo Start=\n";
   for (auto PII : this->PHIInfo) {
     PHIInfoElementT &Element = *PII;
     dbgs() << "Dest: " << PrintReg(Element.DestReg, TRI)
            << " Sources: {";
     for (auto &SI : Element.Sources) {
       dbgs() << PrintReg(SI.first, TRI) << "(BB#"
              << SI.second->getNumber() << "),";
     }
     dbgs() << "}\n";
   }
   dbgs() << "=PHIInfo End=\n";
 }
+#endif
 
 void PHILinearize::clear() { PHIInfo = PHIInfoT(); }
 
 PHILinearize::dest_iterator PHILinearize::dests_begin() {
   return PHILinearizeDestIterator(PHIInfo.begin());
 }
 
 PHILinearize::dest_iterator PHILinearize::dests_end() {
for (auto &II : *Succ) {
             addLiveOut(PHIReg);
           }
         }
       }
     }
   }
 }
 
+#ifndef NDEBUG
 void LinearizedRegion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
   OS << "Linearized Region {";
   bool IsFirst = true;
   for (const auto &MBB : MBBs) {
     if (IsFirst) {
       IsFirst = false;
     } else {
       OS << " ,";
     }
     OS << MBB->getNumber();
   }
   OS << "} (" << Entry->getNumber() << ", "
      << (Exit == nullptr ? -1 : Exit->getNumber())
      << "): In:" << PrintReg(getBBSelectRegIn(), TRI)
      << " Out:" << PrintReg(getBBSelectRegOut(), TRI) << " {";
   for (auto &LI : LiveOuts) {
     OS << PrintReg(LI, TRI) << " ";
   }
   OS << "} \n";
 }
+#endif
 
 unsigned LinearizedRegion::getBBSelectRegIn() {
   return getRegionMRT()->getBBSelectRegIn();
 }
 
 unsigned LinearizedRegion::getBBSelectRegOut() {
   return getRegionMRT()->getBBSelectRegOut();
 }

lib/Target/AMDGPU/AMDILCFGStructurizer.cpp

DEBUG(
       dbgs() << " not working\n";
     );
     DownBlk = (DownBlk->succ_size() == 1) ? (*DownBlk->succ_begin()) : nullptr;
   } // walk down the postDomTree
 
   return Num;
 }
 
+#ifndef NDEBUG
 void AMDGPUCFGStructurizer::showImproveSimpleJumpintoIf(
     MachineBasicBlock *HeadMBB, MachineBasicBlock *TrueMBB,
     MachineBasicBlock *FalseMBB, MachineBasicBlock *LandMBB, bool Detail) {
   dbgs() << "head = BB" << HeadMBB->getNumber()
          << " size = " << HeadMBB->size();
   if (Detail) {
     dbgs() << "\n";
     HeadMBB->print(dbgs());
if (Detail) {
       dbgs() << "\n";
       LandMBB->print(dbgs());
       dbgs() << "\n";
     }
   }
 
   dbgs() << "\n";
 }
+#endif
 
 int AMDGPUCFGStructurizer::improveSimpleJumpintoIf(MachineBasicBlock *HeadMBB,
     MachineBasicBlock *TrueMBB, MachineBasicBlock *FalseMBB,
     MachineBasicBlock **LandMBBPtr) {
   bool MigrateTrue = false;
   bool MigrateFalse = false;
 
   MachineBasicBlock *LandBlk = *LandMBBPtr;

lib/Target/Hexagon/HexagonConstPropagation.cpp

uint32_t LatticeCell::properties() const {
   for (unsigned i = 1; i < size(); ++i) {
     if (Ps == ConstantProperties::Unknown)
       break;
     Ps &= ConstantProperties::deduce(Values[i]);
   }
   return Ps;
 }
 
+#ifndef NDEBUG
 void MachineConstPropagator::CellMap::print(raw_ostream &os,
       const TargetRegisterInfo &TRI) const {
   for (auto &I : Map)
     dbgs() << "  " << PrintReg(I.first, &TRI) << " -> " << I.second << '\n';
 }
+#endif
 
 void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
   const MachineBasicBlock *MB = PN.getParent();
   unsigned MBN = MB->getNumber();
   DEBUG(dbgs() << "Visiting FI(BB#" << MBN << "): " << PN);
 
   const MachineOperand &MD = PN.getOperand(0);
   Register DefR(MD);

lib/Transforms/IPO/SampleProfile.cpp

 
 /// Returns the line offset to the start line of the subprogram.
 /// We assume that a single function will not exceed 65535 LOC.
 unsigned SampleProfileLoader::getOffset(const DILocation *DIL) const {
   return (DIL->getLine() - DIL->getScope()->getSubprogram()->getLine()) &
          0xffff;
 }
 
+#ifndef NDEBUG
 /// \brief Print the weight of edge \p E on stream \p OS.
 ///
 /// \param OS  Stream to emit the output to.
 /// \param E  Edge to print.
 void SampleProfileLoader::printEdgeWeight(raw_ostream &OS, Edge E) {
   OS << "weight[" << E.first->getName() << "->" << E.second->getName()
      << "]: " << EdgeWeights[E] << "\n";
 }

 /// \param OS  Stream to emit the output to.
 /// \param BB  Block to print.
 void SampleProfileLoader::printBlockWeight(raw_ostream &OS,
                                            const BasicBlock *BB) const {
   const auto &I = BlockWeights.find(BB);
   uint64_t W = (I == BlockWeights.end() ? 0 : I->second);
   OS << "weight[" << BB->getName() << "]: " << W << "\n";
 }
+#endif
 
 /// \brief Get the weight for an instruction.
 ///
 /// The "weight" of an instruction \p Inst is the number of samples
 /// collected on that instruction at runtime. To retrieve it, we
 /// need to compute the line number of \p Inst relative to the start of its
 /// function. We use HeaderLineno to compute the offset. We then
 /// look up the samples collected for \p Inst using BodySamples.

lib/Transforms/Scalar/GuardWidening.cpp

PreservedAnalyses GuardWideningPass::run(Function &F,
   if (!GuardWideningImpl(DT, PDT, LI).run())
     return PreservedAnalyses::all();
 
   PreservedAnalyses PA;
   PA.preserveSet<CFGAnalyses>();
   return PA;
 }
 
+#ifndef NDEBUG
 StringRef GuardWideningImpl::scoreTypeToString(WideningScore WS) {
   switch (WS) {
   case WS_IllegalOrNegative:
     return "IllegalOrNegative";
   case WS_Neutral:
     return "Neutral";
   case WS_Positive:
     return "Positive";
   case WS_VeryPositive:
     return "VeryPositive";
   }
 
   llvm_unreachable("Fully covered switch above!");
 }
+#endif
 
 char GuardWideningLegacyPass::ID = 0;
 
 INITIALIZE_PASS_BEGIN(GuardWideningLegacyPass, "guard-widening", "Widen guards",
                       false, false)
 INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(PostDominatorTreeWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
 INITIALIZE_PASS_END(GuardWideningLegacyPass, "guard-widening", "Widen guards",
                     false, false)
 
 FunctionPass *llvm::createGuardWideningPass() {
   return new GuardWideningLegacyPass();
 }

lib/Transforms/Scalar/LoopStrengthReduce.cpp

public:
   SmallBitVector UsedByIndices;
 
   void print(raw_ostream &OS) const;
   void dump() const;
 };
 
 } // end anonymous namespace
 
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 void RegSortData::print(raw_ostream &OS) const {
   OS << "[NumUses=" << UsedByIndices.count() << ']';
 }
 
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD void RegSortData::dump() const {
   print(errs()); errs() << '\n';
 }
 #endif
 
 namespace {
 
 /// Map register candidates to information about how they are used.

 /// Choose the lower cost.
 bool Cost::isLess(Cost &Other, const TargetTransformInfo &TTI) {
   if (InsnsCost.getNumOccurrences() > 0 && InsnsCost &&
       C.Insns != Other.C.Insns)
     return C.Insns < Other.C.Insns;
   return TTI.isLSRCostLess(C, Other.C);
 }
 
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 void Cost::print(raw_ostream &OS) const {
   if (InsnsCost)
     OS << C.Insns << " instruction" << (C.Insns == 1 ? " " : "s ");
   OS << C.NumRegs << " reg" << (C.NumRegs == 1 ? "" : "s");
   if (C.AddRecCost != 0)
     OS << ", with addrec cost " << C.AddRecCost;
   if (C.NumIVMuls != 0)
     OS << ", plus " << C.NumIVMuls << " IV mul"
        << (C.NumIVMuls == 1 ? "" : "s");
   if (C.NumBaseAdds != 0)
     OS << ", plus " << C.NumBaseAdds << " base add"
        << (C.NumBaseAdds == 1 ? "" : "s");
   if (C.ScaleCost != 0)
     OS << ", plus " << C.ScaleCost << " scale cost";
   if (C.ImmCost != 0)
     OS << ", plus " << C.ImmCost << " imm cost";
   if (C.SetupCost != 0)
     OS << ", plus " << C.SetupCost << " setup cost";
 }
 
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD void Cost::dump() const {
   print(errs()); errs() << '\n';
 }
 #endif
 
 LSRFixup::LSRFixup()
   : UserInst(nullptr), OperandValToReplace(nullptr),
     Offset(0) {}
WorkItem(size_t LI, int64_t I, const SCEV *R)
     : LUIdx(LI), Imm(I), OrigReg(R) {}
 
   void print(raw_ostream &OS) const;
   void dump() const;
 };
 
 } // end anonymous namespace
 
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 void WorkItem::print(raw_ostream &OS) const {
   OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx
      << " , add offset " << Imm;
 }
 
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD void WorkItem::dump() const {
   print(errs()); errs() << '\n';
 }
 #endif
 
 /// Look for registers which are a constant distance apart and try to form reuse
 /// opportunities between them.
 void LSRInstance::GenerateCrossUseConstantOffsets() {
for (const LSRUse &LU : Uses) {
     for (const Formula &F : LU.Formulae) {
       OS << "    ";
       F.print(OS);
       OS << '\n';
     }
   }
 }
 
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 void LSRInstance::print(raw_ostream &OS) const {
   print_factors_and_types(OS);
   print_fixups(OS);
   print_uses(OS);
 }
 
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD void LSRInstance::dump() const {
   print(errs()); errs() << '\n';
 }
 #endif
 
 namespace {
 
 class LoopStrengthReduce : public LoopPass {