[MIPS] Implement support for -mstack-alignment.

[bsdjhb]

Summary

This is modeled on the implementation for x86 which stores the command line
option in a 'StackAlignOverride' field in MipsSubtarget and then uses this
to compute a 'stackAlignment' value in
MipsSubtarget::initializeSubtargetDependencies.

The stackAlignment() method in MipsSubTarget is renamed to getStackAlignment()
and returns the computed 'stackAlignment'.

[bsdjhb]

I don't have a test for this yet. My actual use case is a MIPS-based CPU which has 256 bit registers which require 32-byte alignment. This requires the stack to be 32-byte aligned, and using this patch with '-mstack-alignment=32' permits these registers to be spilled onto the stack without alignment exceptions.

It seems that the only tests that use -mstack-alignment on x86 are written in IR (with which I'm not really familiar) but are geared towards a similar case for AVX registers. If it is possible to come up with IR that when assembled results in 'daddui sp,sp,-48' when assembled normally, then we could have a test to verify it uses '-64' when -mstack-alignment=32 is used and -48 otherwise.

[sdardis]

In D35874#821062, @bsdjhb wrote:

If it is possible to come up with IR that when assembled results in 'daddui sp,sp,-48' when assembled normally, then we could have a test to verify it uses '-64' when -mstack-alignment=32 is used and -48 otherwise.

See test/CodeGen/Mips/stack-alignment.ll, you'll need to modify that to accept whatever option is produced by -mstack-alignment.

lib/Target/Mips/MipsSubtarget.cpp

163

That looks incorrect. Instead, if the ABI is N32 or N64, then the stack alignment is 16, otherwise of O32 it is 8.

At least according to GCC and the documentation I have to hand.

Can you split this patch into two parts, the first one that fixes the bug and the second which implements this new feature?

[bsdjhb]

• Rebase on top of D36326.
• Add tests.

[sdardis]

lib/Target/Mips/MipsSubtarget.cpp

166

Can you introduce an assertion here that the ABI is O32? If EABI support is ever brought back or another MIPS abi is introduced, I'd prefer debug builds complain loudly.

[bsdjhb]

• Rebase on updated D36326.
• clang-format and add an assertion.

[sdardis]

lib/Target/Mips/MipsSubtarget.cpp

166

That assert needs a && "Unknown ABI for stack alignment!".

test/CodeGen/Mips/stack-alignment.ll

11

This need to be doubled up to A32-32, A32-64 with the appropriate (d)addiu instructions.

[bsdjhb]

• Add a message to the assertion.

[sdardis]

LGTM with a comment fix.

lib/Target/Mips/MipsSubtarget.h

162

"Override the stack alignmen.t" -> "The overridden stack alignment."

lib/Target/Mips/Mips16FrameLowering.cpp

 #include "llvm/Target/TargetFrameLowering.h"
 #include <cassert>
 #include <cstdint>
 #include <vector>
 
 using namespace llvm;
 
 Mips16FrameLowering::Mips16FrameLowering(const MipsSubtarget &STI)
-    : MipsFrameLowering(STI, STI.stackAlignment()) {}
+    : MipsFrameLowering(STI, STI.getStackAlignment()) {}
 
 void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
   assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const Mips16InstrInfo &TII =
       *static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
   MachineBasicBlock::iterator MBBI = MBB.begin();

lib/Target/Mips/MipsAsmPrinter.cpp

void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
   // that we'd have constructed. Module level directives aren't LTO
   // clean anyhow.
   // FIXME: For ifunc related functions we could iterate over and look
   // for a feature string that doesn't match the default one.
   const Triple &TT = TM.getTargetTriple();
   StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU());
   StringRef FS = TM.getTargetFeatureString();
   const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
-  const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM);
+  const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM, 0);
 
   bool IsABICalls = STI.isABICalls();
   const MipsABIInfo &ABI = MTM.getABI();
   if (IsABICalls) {
     TS.emitDirectiveAbiCalls();
     // FIXME: This condition should be a lot more complicated that it is here.
     //        Ideally it should test for properties of the ABI and not the ABI
     //        itself.

lib/Target/Mips/MipsSEFrameLowering.cpp

if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
     TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset);
     return true;
   }
 
   return false;
 }
 
 MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)
-    : MipsFrameLowering(STI, STI.stackAlignment()) {}
+    : MipsFrameLowering(STI, STI.getStackAlignment()) {}
 
 void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
   assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
   MachineFrameInfo &MFI    = MF.getFrameInfo();
   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 
   const MipsSEInstrInfo &TII =

lib/Target/Mips/MipsSubtarget.h

class MipsSubtarget : public MipsGenSubtargetInfo {
   bool DisableMadd4;
 
   // HasMT -- support MT ASE.
   bool HasMT;
 
   // Disable use of the `jal` instruction.
   bool UseLongCalls = false;
 
+  /// The minimum alignment known to hold of the stack frame on
+  /// entry to the function and which must be maintained by every function.
+  unsigned stackAlignment;
+
+  /// Override the stack alignment.
+  unsigned StackAlignOverride;
+
   InstrItineraryData InstrItins;
 
   // We can override the determination of whether we are in mips16 mode
   // as from the command line
   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
 
   const MipsTargetMachine &TM;
 
public:
   bool isABI_N32() const;
   bool isABI_O32() const;
   const MipsABIInfo &getABI() const;
   bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
 
   /// This constructor initializes the data members to match that
   /// of the specified triple.
   MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
-                const MipsTargetMachine &TM);
+                const MipsTargetMachine &TM, unsigned StackAlignOverride);
 
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   bool hasMips1() const { return MipsArchVersion >= Mips1; }
   bool hasMips2() const { return MipsArchVersion >= Mips2; }
   bool hasMips3() const { return MipsArchVersion >= Mips3; }
public:
   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
 
   bool isXRaySupported() const override { return true; }
 
   // for now constant islands are on for the whole compilation unit but we only
   // really use them if in addition we are in mips16 mode
   static bool useConstantIslands();
 
-  unsigned stackAlignment() const {
-    return isABI_N32() || isABI_N64() ? 16 : 8;
-  }
+  unsigned getStackAlignment() const { return stackAlignment; }
 
   // Grab relocation model
   Reloc::Model getRelocationModel() const;
 
   MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
                                                  const TargetMachine &TM);
 
   /// Does the system support unaligned memory access.

lib/Target/Mips/MipsSubtarget.cpp

 
 static cl::opt<bool>
     GPOpt("mgpopt", cl::Hidden,
           cl::desc("Enable gp-relative addressing of mips small data items"));
 
 void MipsSubtarget::anchor() { }
 
 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
-                             bool little, const MipsTargetMachine &TM)
+                             bool little, const MipsTargetMachine &TM,
+                             unsigned StackAlignOverride)
     : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
       IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
       NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
       IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
       HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
       HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
       InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
       HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
       Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
-      HasEVA(false), DisableMadd4(false), HasMT(false), TM(TM),
-      TargetTriple(TT), TSInfo(),
-      InstrInfo(
-          MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
+      HasEVA(false), DisableMadd4(false), HasMT(false),
+      StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
+      TSInfo(), InstrInfo(MipsInstrInfo::create(
+                    initializeSubtargetDependencies(CPU, FS, TM))),
       FrameLowering(MipsFrameLowering::create(*this)),
       TLInfo(MipsTargetLowering::create(TM, *this)) {
 
   if (MipsArchVersion == MipsDefault)
     MipsArchVersion = Mips32;
 
   // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
   // been tested and currently exist for the integrated assembler only.
MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUName);
 
   if (InMips16Mode && !IsSoftFloat)
     InMips16HardFloat = true;
 
+  if (StackAlignOverride)
+    stackAlignment = StackAlignOverride;
+  else if (isABI_N32() || isABI_N64())
+    stackAlignment = 16;
+  else {
+    assert(isABI_O32() && "Unknown ABI for stack alignment!");
+    stackAlignment = 8;
+  }
+
   return *this;
 }
 
 bool MipsSubtarget::useConstantIslands() {
   DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
   return Mips16ConstantIslands;
 }
 
 Reloc::Model MipsSubtarget::getRelocationModel() const {
   return TM.getRelocationModel();
 }
 
 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }

lib/Target/Mips/MipsTargetMachine.cpp

MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
                                      Optional<CodeModel::Model> CM,
                                      CodeGenOpt::Level OL, bool JIT,
                                      bool isLittle)
     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
                         CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
                         getEffectiveCodeModel(CM), OL),
       isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()),
       ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
-      Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
+      Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this,
+                                           Options.StackAlignmentOverride),
       NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
-                        isLittle, *this),
+                        isLittle, *this, Options.StackAlignmentOverride),
       Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
-                      isLittle, *this) {
+                      isLittle, *this, Options.StackAlignmentOverride) {
   Subtarget = &DefaultSubtarget;
   initAsmInfo();
 }
 
 MipsTargetMachine::~MipsTargetMachine() = default;
 
 void MipsebTargetMachine::anchor() {}
 
MipsTargetMachine::getSubtargetImpl(const Function &F) const {
 
   auto &I = SubtargetMap[CPU + FS];
   if (!I) {
     // This needs to be done before we create a new subtarget since any
     // creation will depend on the TM and the code generation flags on the
     // function that reside in TargetOptions.
     resetTargetOptions(F);
     I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle,
-                                         *this);
+                                         *this, Options.StackAlignmentOverride);
   }
   return I.get();
 }
 
 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
   DEBUG(dbgs() << "resetSubtarget\n");
 
   Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));

test/CodeGen/Mips/stack-alignment.ll

 ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
+; RUN: llc -march=mipsel -stack-alignment=32 < %s | FileCheck %s -check-prefix=A32-32
 ; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=32
 ; RUN: llc -march=mips64el -mcpu=mips3 < %s | FileCheck %s -check-prefix=64
 ; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64
 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
+; RUN: llc -march=mips64el -mcpu=mips64 -stack-alignment=32 < %s | FileCheck %s -check-prefix=A32-64
 
 ; 32:      addiu  $sp, $sp, -8
 ; 64:      daddiu  $sp, $sp, -16
+; A32-32:  addiu  $sp, $sp, -32
+; A32-64:  daddiu  $sp, $sp, -32
 
 define i32 @foo1() #0 {
 entry:
   ret i32 14
 }
 
 attributes #0 = { "no-frame-pointer-elim"="true" }