This patch adds the following
- Adds a skeleton scheduler model for AMD Znver1.
- Introduces the znver1 execution units and pipes.
- Caters the instructions based on the generic scheduler classes.
- Further additions to the scheduler model with instruction itineraries will be carried out incrementally based on a. Instructions types b. Registers used
- Since itineraries are not added based on instructions, throughput information are bound to change when incremental changes are added.
- Scheduler testcases are modified accordingly to suit the new model.