[mips][mt][5/7] Add support for fork and yield instructions.

[atanasyan]

LGTM

lib/Target/Mips/MipsMTInstrFormats.td

class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
   let Inst{25-21} = 0b01011;  // MFMC0
   let Inst{20-16} = rt;
   let Inst{15-11} = Op1.Value;
   let Inst{10-6}  = Op2.Value;
   let Inst{5}     = sc.Value;
   let Inst{4-3}   = 0b00;
   let Inst{2-0}   = 0b001;
 }
+
+class SPECIAL3_MT_FORK : MipsMTInst {
+  bits<32> Inst;
+
+  bits<5> rs;
+  bits<5> rt;
+  bits<5> rd;
+  let Inst{31-26} = 0b011111; // SPECIAL3
+  let Inst{25-21} = rs;
+  let Inst{20-16} = rt;
+  let Inst{15-11} = rd;
+  let Inst{10-6}  = 0b00000;
+  let Inst{5-0}   = 0b001000; // FORK
+}
+
+class SPECIAL3_MT_YIELD : MipsMTInst {
+  bits<32> Inst;
+
+  bits<5> rs;
+  bits<5> rd;
+  let Inst{31-26} = 0b011111; // SPECIAL3
+  let Inst{25-21} = rs;
+  let Inst{20-16} = 0b00000;
+  let Inst{15-11} = rd;
+  let Inst{10-6}  = 0b00000;
+  let Inst{5-0}   = 0b001001; // FORK
+}

lib/Target/Mips/MipsMTInstrInfo.td

class EMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,
                               OPCODE_SC_E>;
 
 class DVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,
                                OPCODE_SC_D>;
 
 class EVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,
                                OPCODE_SC_E>;
 
+class FORK_ENC : SPECIAL3_MT_FORK;
+
+class YIELD_ENC : SPECIAL3_MT_YIELD;
+
 //===----------------------------------------------------------------------===//
 // MIPS MT Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 class MT_1R_DESC_BASE<string instr_asm, InstrItinClass Itin = NoItinerary> {
   dag OutOperandList = (outs GPR32Opnd:$rt);
   dag InOperandList = (ins);
   string AsmString = !strconcat(instr_asm, "\t$rt");
   list<dag> Pattern = [];
   InstrItinClass Itinerary = Itin;
 }
 
+class FORK_DESC {
+  dag OutOperandList = (outs GPR32Opnd:$rs, GPR32Opnd:$rd);
+  dag InOperandList = (ins GPR32Opnd:$rt);
+  string AsmString = "fork\t$rd, $rs, $rt";
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = II_FORK;
+}
+
+class YIELD_DESC {
+  dag OutOperandList = (outs GPR32Opnd:$rd);
+  dag InOperandList = (ins GPR32Opnd:$rs);
+  string AsmString = "yield\t$rd, $rs";
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = II_YIELD;
+}
+
 class DMT_DESC : MT_1R_DESC_BASE<"dmt", II_DMT>;
 
 class EMT_DESC : MT_1R_DESC_BASE<"emt", II_EMT>;
 
 class DVPE_DESC : MT_1R_DESC_BASE<"dvpe", II_DVPE>;
 
 class EVPE_DESC : MT_1R_DESC_BASE<"evpe", II_EVPE>;
 
 //===----------------------------------------------------------------------===//
 // MIPS MT Instruction Definitions
 //===----------------------------------------------------------------------===//
 let hasSideEffects = 1, isNotDuplicable = 1,
     AdditionalPredicates = [NotInMicroMips] in {
   def DMT : DMT_ENC, DMT_DESC, ASE_MT;
 
   def EMT : EMT_ENC, EMT_DESC, ASE_MT;
 
   def DVPE : DVPE_ENC, DVPE_DESC, ASE_MT;
 
   def EVPE : EVPE_ENC, EVPE_DESC, ASE_MT;
+
+  def FORK : FORK_ENC, FORK_DESC, ASE_MT;
+
+  def YIELD : YIELD_ENC, YIELD_DESC, ASE_MT;
 }
 
 //===----------------------------------------------------------------------===//
 // MIPS MT Instruction Definitions
 //===----------------------------------------------------------------------===//
 
 let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<"dmt", (DMT ZERO), 1>, ASE_MT;
 
   def : MipsInstAlias<"emt", (EMT ZERO), 1>, ASE_MT;
 
   def : MipsInstAlias<"dvpe", (DVPE ZERO), 1>, ASE_MT;
 
   def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT;
+
+  def : MipsInstAlias<"yield $rs", (YIELD ZERO, GPR32Opnd:$rs), 1>, ASE_MT;
 }

lib/Target/Mips/MipsSchedule.td

 def II_DSHD             : InstrItinClass;
 def II_DSUBU            : InstrItinClass;
 def II_DSUB             : InstrItinClass;
 def II_DVPE             : InstrItinClass;
 def II_EMT              : InstrItinClass;
 def II_EVPE             : InstrItinClass;
 def II_EXT              : InstrItinClass; // Any EXT instruction
 def II_FLOOR            : InstrItinClass;
+def II_FORK             : InstrItinClass;
 def II_INS              : InstrItinClass; // Any INS instruction
 def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo.
 def II_J                : InstrItinClass;
 def II_JAL              : InstrItinClass;
 def II_JALR             : InstrItinClass;
 def II_JALR_HB          : InstrItinClass;
 def II_JALRC            : InstrItinClass;
 def II_JALRS            : InstrItinClass;

 def II_LLE              : InstrItinClass;
 def II_SCE              : InstrItinClass;
 def II_TLBINV           : InstrItinClass;
 def II_TLBINVF          : InstrItinClass;
 def II_WRPGPR           : InstrItinClass;
 def II_RDPGPR           : InstrItinClass;
 def II_DVP              : InstrItinClass;
 def II_EVP              : InstrItinClass;
+def II_YIELD            : InstrItinClass;
 
 //===----------------------------------------------------------------------===//
 // Mips Generic instruction itineraries.
 //===----------------------------------------------------------------------===//
 def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
   InstrItinData<IIM16Alu           , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_ADDI            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_ADDIU           , [InstrStage<1,  [ALU]>]>,
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
   InstrItinData<II_DSBH            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DSHD            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DCLO            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DCLZ            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DVPE            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_EMT             , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_EVPE            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_EXT             , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_FORK            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_INS             , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_LUI             , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_MOVE            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_MOVF            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_MOVN            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_MOVN_S          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_MOVN_D          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_MOVT            , [InstrStage<1,  [ALU]>]>,
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
   InstrItinData<II_PREFE           , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_TLBINV          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_TLBINVF         , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_LLE             , [InstrStage<3,  [ALU]>]>,
   InstrItinData<II_SCE             , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_WRPGPR          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_RDPGPR          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DVP             , [InstrStage<1,  [ALU]>]>,
-  InstrItinData<II_EVP             , [InstrStage<1,  [ALU]>]>
+  InstrItinData<II_EVP             , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_YIELD           , [InstrStage<5,  [ALU]>]>
 ]>;

lib/Target/Mips/MipsScheduleGeneric.td

 // =============
 
 def GenericCOP0 : ProcResource<1> { let BufferSize = 1; }
 
 def GenericIssueCOP0 : ProcResource<1> { let Super = GenericCOP0; }
 def GenericWriteCOP0TLB : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 4; }
 def GenericWriteCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 3; }
 def GenericReadCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 2; }
-def GnereicReadWritePGPR : SchedWriteRes<[GenericIssueCOP0]>;
+def GenericReadWritePGPR : SchedWriteRes<[GenericIssueCOP0]>;
+def GenericReadWriteCOP0Long : SchedWriteRes<[GenericIssueCOP0]> {
+  let Latency = 5;
+}
+def GenericWriteCOP0Short : SchedWriteRes<[GenericIssueCOP0]>;
 
 def : ItinRW<[GenericWriteCOP0TLB], [II_TLBP, II_TLBR, II_TLBWI, II_TLBWR]>;
 def : ItinRW<[GenericWriteCOP0TLB], [II_TLBINV, II_TLBINVF]>;
 
 def : ItinRW<[GenericReadCOP0], [II_MFC0]>;
 def : ItinRW<[GenericWriteCOP0], [II_MTC0]>;
 
 def : ItinRW<[GenericWriteCOP0], [II_EVP, II_DVP]>;

 
 def : ItinRW<[GenericWriteLoad], [II_LWLE, II_LWRE]>;
 
 // MIPS MT instructions
 // ====================
 
 def : ItinRW<[GenericWriteMove], [II_DMT, II_DVPE, II_EMT, II_EVPE]>;
 
+def : ItinRW<[GenericReadWriteCOP0Long], [II_YIELD]>;
+def : ItinRW<[GenericWriteCOP0Short], [II_FORK]>;
 
 // MIPS32R6 and MIPS16e
 // ====================
 
 def : ItinRW<[GenericWriteLoad], [II_LWPC]>;
 
 // MIPS64R6
 // ====================

test/MC/Disassembler/Mips/mt/valid-r2-el.txt

 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+mt | FileCheck %s
 0xc1 0x0b 0x60 0x41  # CHECK: dmt
 0xc1 0x0b 0x65 0x41  # CHECK: dmt $5
 0xe1 0x0b 0x60 0x41  # CHECK: emt
 0xe1 0x0b 0x64 0x41  # CHECK: emt $4
 0x01 0x00 0x60 0x41  # CHECK: dvpe
 0x01 0x00 0x66 0x41  # CHECK: dvpe  $6
 0x21 0x00 0x60 0x41  # CHECK: evpe
 0x21 0x00 0x64 0x41  # CHECK: evpe  $4
+0x08 0x10 0x65 0x7c  # CHECK: fork  $2, $3, $5
+0x09 0x00 0x80 0x7c  # CHECK: yield  $4
+0x09 0x20 0xa0 0x7c  # CHECK: yield $4, $5
 

test/MC/Disassembler/Mips/mt/valid-r2.txt

 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+mt | FileCheck %s
 0x41 0x60 0x0b 0xc1  # CHECK: dmt
 0x41 0x65 0x0b 0xc1  # CHECK: dmt $5
 0x41 0x60 0x0b 0xe1  # CHECK: emt
 0x41 0x64 0x0b 0xe1  # CHECK: emt $4
 0x41 0x60 0x00 0x01  # CHECK: dvpe
 0x41 0x66 0x00 0x01  # CHECK: dvpe  $6
 0x41 0x60 0x00 0x21  # CHECK: evpe
 0x41 0x64 0x00 0x21  # CHECK: evpe  $4
+0x7c 0x65 0x10 0x08  # CHECK: fork  $2, $3, $5
+0x7c 0x80 0x00 0x09  # CHECK: yield  $4
+0x7c 0xa0 0x20 0x09  # CHECK: yield $4, $5
 

test/MC/Mips/mt/valid.s

 # RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s \
 # RUN:   | FileCheck %s
   dmt           # CHECK:  dmt         # encoding: [0x41,0x60,0x0b,0xc1]
   dmt $5        # CHECK:  dmt $5      # encoding: [0x41,0x65,0x0b,0xc1]
   emt           # CHECK:  emt         # encoding: [0x41,0x60,0x0b,0xe1]
   emt $4        # CHECK:  emt $4      # encoding: [0x41,0x64,0x0b,0xe1]
   dvpe          # CHECK:  dvpe        # encoding: [0x41,0x60,0x00,0x01]
   dvpe $6       # CHECK:  dvpe  $6    # encoding: [0x41,0x66,0x00,0x01]
   evpe          # CHECK:  evpe        # encoding: [0x41,0x60,0x00,0x21]
   evpe $4       # CHECK:  evpe  $4    # encoding: [0x41,0x64,0x00,0x21]
-
+  fork $2, $3, $5 # CHECK:  fork  $2, $3, $5 # encoding: [0x7c,0x65,0x10,0x08]
+  yield $4        # CHECK:  yield  $4        # encoding: [0x7c,0x80,0x00,0x09]
+  yield $4, $5    # CHECK:  yield $4, $5     # encoding: [0x7c,0xa0,0x20,0x09]