[CodeGen] Rename DEBUG_TYPE to match passnames

[evandro]

Summary

Rename missing DEBUG_TYPE "machine-scheduler" from backend files, assuming that these DEBUG_TYPE were forgotten in the original patch.

[MatzeB]

Yep, that was an oversight. Thanks for fixing!

llvm/trunk/lib/CodeGen/MacroFusion.cpp

 #include "llvm/CodeGen/MachineScheduler.h"
 #include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CodeGen/ScheduleDAGMutation.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetInstrInfo.h"
 
-#define DEBUG_TYPE "misched"
+#define DEBUG_TYPE "machine-scheduler"
 
 STATISTIC(NumFused, "Number of instr pairs fused");
 
 using namespace llvm;
 
 static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
   cl::desc("Enable scheduling for macro fusion."), cl::init(true));
 

llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

 #include <cassert>
 #include <iterator>
 #include <string>
 #include <utility>
 #include <vector>
 
 using namespace llvm;
 
-#define DEBUG_TYPE "misched"
+#define DEBUG_TYPE "machine-scheduler"
 
 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
     cl::ZeroOrMore, cl::init(false),
     cl::desc("Enable use of AA during MI DAG construction"));
 
 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
     cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"));
 

llvm/trunk/lib/Target/AMDGPU/GCNIterativeScheduler.cpp

 //===----------------------------------------------------------------------===//
 
 #include "GCNIterativeScheduler.h"
 #include "GCNSchedStrategy.h"
 #include "SIMachineFunctionInfo.h"
 
 using namespace llvm;
 
-#define DEBUG_TYPE "misched"
+#define DEBUG_TYPE "machine-scheduler"
 
 namespace llvm {
   std::vector<const SUnit*> makeMinRegSchedule(ArrayRef<const SUnit*> TopRoots,
     const ScheduleDAG &DAG);
 }
 
 // shim accessors for different order containers
 static inline MachineInstr *getMachineInstr(MachineInstr *MI) {

llvm/trunk/lib/Target/AMDGPU/GCNMinRegStrategy.cpp

 /// \file
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/ScheduleDAG.h"
 
 using namespace llvm;
 
-#define DEBUG_TYPE "misched"
+#define DEBUG_TYPE "machine-scheduler"
 
 namespace {
 class GCNMinRegScheduler {
   struct Candidate : ilist_node<Candidate> {
     const SUnit *SU;
     int Priority;
 
     Candidate(const SUnit *SU_, int Priority_ = 0)

llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "GCNRegPressure.h"
 #include "llvm/CodeGen/RegisterPressure.h"
 
 using namespace llvm;
 
-#define DEBUG_TYPE "misched"
+#define DEBUG_TYPE "machine-scheduler"
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD
 void llvm::printLivesAt(SlotIndex SI,
                         const LiveIntervals &LIS,
                         const MachineRegisterInfo &MRI) {
   dbgs() << "Live regs at " << SI << ": "
          << *LIS.getInstructionFromIndex(SI);

llvm/trunk/lib/Target/AMDGPU/GCNSchedStrategy.cpp

 #include "GCNSchedStrategy.h"
 #include "AMDGPUSubtarget.h"
 #include "SIInstrInfo.h"
 #include "SIMachineFunctionInfo.h"
 #include "SIRegisterInfo.h"
 #include "llvm/CodeGen/RegisterClassInfo.h"
 #include "llvm/Support/MathExtras.h"
 
-#define DEBUG_TYPE "misched"
+#define DEBUG_TYPE "machine-scheduler"
 
 using namespace llvm;
 
 GCNMaxOccupancySchedStrategy::GCNMaxOccupancySchedStrategy(
     const MachineSchedContext *C) :
     GenericScheduler(C), TargetOccupancy(0), MF(nullptr) { }
 
 static unsigned getMaxWaves(unsigned SGPRs, unsigned VGPRs,

llvm/trunk/lib/Target/AMDGPU/R600MachineScheduler.cpp

 #include "R600InstrInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
-#define DEBUG_TYPE "misched"
+#define DEBUG_TYPE "machine-scheduler"
 
 void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
   assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness");
   DAG = static_cast<ScheduleDAGMILive*>(dag);
   const R600Subtarget &ST = DAG->MF.getSubtarget<R600Subtarget>();
   TII = static_cast<const R600InstrInfo*>(DAG->TII);
   TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
   VLIW5 = !ST.hasCaymanISA();

llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp

 #include <cassert>
 #include <map>
 #include <set>
 #include <utility>
 #include <vector>
 
 using namespace llvm;
 
-#define DEBUG_TYPE "misched"
+#define DEBUG_TYPE "machine-scheduler"
 
 // This scheduler implements a different scheduling algorithm than
 // GenericScheduler.
 //
 // There are several specific architecture behaviours that can't be modelled
 // for GenericScheduler:
 // . When accessing the result of an SGPR load instruction, you have to wait
 // for all the SGPR load instructions before your current instruction to

llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp

 
 // Check if the scheduler should penalize instructions that are available to
 // early due to a zero-latency dependence.
 static cl::opt<bool> CheckEarlyAvail("check-early-avail", cl::Hidden,
     cl::ZeroOrMore, cl::init(true));
 
 using namespace llvm;
 
-#define DEBUG_TYPE "misched"
+#define DEBUG_TYPE "machine-scheduler"
 
 namespace {
 class HexagonCallMutation : public ScheduleDAGMutation {
 public:
   void apply(ScheduleDAGInstrs *DAG) override;
 private:
   bool shouldTFRICallBind(const HexagonInstrInfo &HII,
                           const SUnit &Inst1, const SUnit &Inst2) const;

llvm/trunk/lib/Target/SystemZ/SystemZHazardRecognizer.cpp

 //
 // ===---------------------------------------------------------------------===//
 
 #include "SystemZHazardRecognizer.h"
 #include "llvm/ADT/Statistic.h"
 
 using namespace llvm;
 
-#define DEBUG_TYPE "misched"
+#define DEBUG_TYPE "machine-scheduler"
 
 // This is the limit of processor resource usage at which the
 // scheduler should try to look for other instructions (not using the
 // critical resource).
 static cl::opt<int> ProcResCostLim("procres-cost-lim", cl::Hidden,
                                    cl::desc("The OOO window for processor "
                                             "resources during scheduling."),
                                    cl::init(8));

llvm/trunk/lib/Target/SystemZ/SystemZMachineScheduler.cpp

 // implementation that looks to optimize decoder grouping and balance the
 // usage of processor resources.
 //===----------------------------------------------------------------------===//
 
 #include "SystemZMachineScheduler.h"
 
 using namespace llvm;
 
-#define DEBUG_TYPE "misched"
+#define DEBUG_TYPE "machine-scheduler"
 
 #ifndef NDEBUG
 // Print the set of SUs
 void SystemZPostRASchedStrategy::SUSet::
 dump(SystemZHazardRecognizer &HazardRec) const {
   dbgs() << "{";
   for (auto &SU : *this) {
     HazardRec.dumpSU(SU, dbgs());