[AMDGPU][mc][gfx9] Added support of op_sel/op_sel_hi for V_MAD_MIX*

[dp]

Summary

See https://bugs.llvm.org//show_bug.cgi?id=33595

[artem.tamazov]

LGTM but please keep at least some handwritten cases in vop3p.s/vop3p-err.s.

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

for (int J = 0; J < 3; ++J) {
     if ((NegLo & (1 << J)) != 0)
       ModVal |= SISrcMods::NEG;
 
     if ((NegHi & (1 << J)) != 0)
       ModVal |= SISrcMods::NEG_HI;
 
     int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
 
-    Inst.getOperand(ModIdx).setImm(ModVal);
+    Inst.getOperand(ModIdx).setImm(Inst.getOperand(ModIdx).getImm() | ModVal);
   }
 }
 
 //===----------------------------------------------------------------------===//
 // dpp
 //===----------------------------------------------------------------------===//
 
 bool AMDGPUOperand::isDPPCtrl() const {

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

 
 def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>;
 def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>;
 def VOP_B32_F16_F16 : VOPProfile <[i32, f16, f16, untyped]>;
 
 def VOP_V2F16_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, v2f16]>;
 def VOP_V2I16_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, v2i16]>;
 
+def VOP_F32_V2F16_V2F16_V2F16 : VOPProfile <[f32, v2f16, v2f16, v2f16]>;
+
 def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
 
 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;

llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td

 // VOP3P Classes
 //===----------------------------------------------------------------------===//
 
 class VOP3PInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> :
   VOP3P_Pseudo<OpName, P,
     !if(P.HasModifiers, getVOP3PModPat<P, node>.ret, getVOP3Pat<P, node>.ret)
 >;
 
-// Non-packed instructions that use the VOP3P encoding. i.e. where
-// omod/abs are used.
+// Non-packed instructions that use the VOP3P encoding.
+// VOP3 neg/abs and VOP3P opsel/opsel_hi modifiers are allowed.
 class VOP3_VOP3PInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> :
-  VOP3P_Pseudo<OpName, P,
-    !if(P.HasModifiers, getVOP3ModPat<P, node>.ret, getVOP3Pat<P, node>.ret)
->;
+  VOP3P_Pseudo<OpName, P> {
+  let InOperandList =
+    (ins
+      FP32InputMods:$src0_modifiers, VCSrc_f32:$src0,
+      FP32InputMods:$src1_modifiers, VCSrc_f32:$src1,
+      FP32InputMods:$src2_modifiers, VCSrc_f32:$src2,
+      clampmod:$clamp,
+      op_sel:$op_sel,
+      op_sel_hi:$op_sel_hi);
+  let AsmOperands =
+    " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp";
+}
 
 let isCommutable = 1 in {
 def V_PK_FMA_F16 : VOP3PInst<"v_pk_fma_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16_V2F16>, fma>;
 def V_PK_ADD_F16 : VOP3PInst<"v_pk_add_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fadd>;
 def V_PK_MUL_F16 : VOP3PInst<"v_pk_mul_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fmul>;
 def V_PK_MAX_F16 : VOP3PInst<"v_pk_max_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fmaxnum>;
 def V_PK_MIN_F16 : VOP3PInst<"v_pk_min_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fminnum>;
 
 def V_PK_ADD_U16 : VOP3PInst<"v_pk_add_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, add>;
 def V_PK_ADD_I16 : VOP3PInst<"v_pk_add_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>>;
 def V_PK_SUB_I16 : VOP3PInst<"v_pk_sub_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, sub>;
 def V_PK_MUL_LO_U16 : VOP3PInst<"v_pk_mul_lo_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, mul>;
 
 def V_PK_MIN_I16 : VOP3PInst<"v_pk_min_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, smin>;
 def V_PK_MIN_U16 : VOP3PInst<"v_pk_min_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, umin>;
 def V_PK_MAX_I16 : VOP3PInst<"v_pk_max_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, smax>;
 def V_PK_MAX_U16 : VOP3PInst<"v_pk_max_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, umax>;
 }
 
 def V_PK_LSHLREV_B16 : VOP3PInst<"v_pk_lshlrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshl_rev>;
 def V_PK_ASHRREV_I16 : VOP3PInst<"v_pk_ashrrev_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, ashr_rev>;
 def V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshr_rev>;
 
 // XXX - Commutable?
-def V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
-def V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>;
-def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>;
+// These are VOP3a-like opcodes which accept no omod.
+// Size of src arguments (16/32) is controlled by op_sel.
+// For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi.
+def V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3_Profile<VOP_F32_V2F16_V2F16_V2F16>>;
+def V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16_V2F16>>;
+def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16_V2F16>>;
 
 
 multiclass VOP3P_Real_vi<bits<10> op> {
   def _vi : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.VI>,
             VOP3Pe <op, !cast<VOP3P_Pseudo>(NAME).Pfl> {
     let AssemblerPredicates = [HasVOP3PInsts];
     let DecoderNamespace = "VI";
   }

llvm/trunk/test/MC/AMDGPU/gfx9_asm_all.s

 v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
 // CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x04]
 
 v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
 // CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x05]
 
 v_cmpx_t_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
 // CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x0e]
+
+v_mad_mix_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0xff,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x04,0x0e,0x1c]
+
+v_mad_mix_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x65,0x04,0x0e,0x1c]
+
+v_mad_mix_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x66,0x04,0x0e,0x1c]
+
+v_mad_mix_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x67,0x04,0x0e,0x1c]
+
+v_mad_mix_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x6a,0x04,0x0e,0x1c]
+
+v_mad_mix_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x6b,0x04,0x0e,0x1c]
+
+v_mad_mix_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x7c,0x04,0x0e,0x1c]
+
+v_mad_mix_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x7e,0x04,0x0e,0x1c]
+
+v_mad_mix_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x7f,0x04,0x0e,0x1c]
+
+v_mad_mix_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xff,0x0f,0x1c]
+
+v_mad_mix_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0c,0x1c]
+
+v_mad_mix_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xcb,0x0c,0x1c]
+
+v_mad_mix_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xcd,0x0c,0x1c]
+
+v_mad_mix_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xcf,0x0c,0x1c]
+
+v_mad_mix_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xd5,0x0c,0x1c]
+
+v_mad_mix_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xd7,0x0c,0x1c]
+
+v_mad_mix_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xf9,0x0c,0x1c]
+
+v_mad_mix_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xfd,0x0c,0x1c]
+
+v_mad_mix_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0xff,0x0c,0x1c]
+
+v_mad_mix_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0xfe,0x1f]
+
+v_mad_mix_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x18]
+
+v_mad_mix_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x96,0x19]
+
+v_mad_mix_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x9a,0x19]
+
+v_mad_mix_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x9e,0x19]
+
+v_mad_mix_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0xaa,0x19]
+
+v_mad_mix_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0xae,0x19]
+
+v_mad_mix_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0xf2,0x19]
+
+v_mad_mix_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0xfa,0x19]
+
+v_mad_mix_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0xfe,0x19]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,0]
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,0,0]
+// CHECK: [0x05,0x48,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,1,0]
+// CHECK: [0x05,0x50,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,1]
+// CHECK: [0x05,0x60,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,1,1]
+// CHECK: [0x05,0x78,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,1,1]
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,0]
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,0,0]
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,1,0]
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,1]
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x3c]
+
+v_mad_mix_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x5c]
+
+v_mad_mix_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x9c]
+
+v_mad_mix_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0xfc]
+
+v_mad_mix_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x41,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x42,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x44,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x47,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0xc0,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0xff,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x04,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x65,0x04,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x66,0x04,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x67,0x04,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x6a,0x04,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x6b,0x04,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x7c,0x04,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x7e,0x04,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x7f,0x04,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0xff,0x0f,0x1c]
+
+v_mad_mixhi_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0c,0x1c]
+
+v_mad_mixhi_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0xcb,0x0c,0x1c]
+
+v_mad_mixhi_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0xcd,0x0c,0x1c]
+
+v_mad_mixhi_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0xcf,0x0c,0x1c]
+
+v_mad_mixhi_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0xd5,0x0c,0x1c]
+
+v_mad_mixhi_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0xd7,0x0c,0x1c]
+
+v_mad_mixhi_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0xf9,0x0c,0x1c]
+
+v_mad_mixhi_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0xfd,0x0c,0x1c]
+
+v_mad_mixhi_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0xff,0x0c,0x1c]
+
+v_mad_mixhi_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0xfe,0x1f]
+
+v_mad_mixhi_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x18]
+
+v_mad_mixhi_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x96,0x19]
+
+v_mad_mixhi_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x9a,0x19]
+
+v_mad_mixhi_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x9e,0x19]
+
+v_mad_mixhi_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0xaa,0x19]
+
+v_mad_mixhi_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0xae,0x19]
+
+v_mad_mixhi_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0xf2,0x19]
+
+v_mad_mixhi_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0xfa,0x19]
+
+v_mad_mixhi_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0xfe,0x19]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,0,0]
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[1,0,0]
+// CHECK: [0x05,0x48,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,1,0]
+// CHECK: [0x05,0x50,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,0,1]
+// CHECK: [0x05,0x60,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[1,1,1]
+// CHECK: [0x05,0x78,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1]
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,0,0]
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0]
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x0c]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0]
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x14]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1]
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x3c]
+
+v_mad_mixhi_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x5c]
+
+v_mad_mixhi_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x9c]
+
+v_mad_mixhi_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0xfc]
+
+v_mad_mixhi_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x41,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x42,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x44,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x47,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0xc0,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0xff,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x04,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x65,0x04,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x66,0x04,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x67,0x04,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x6a,0x04,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x6b,0x04,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x7c,0x04,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x7e,0x04,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x7f,0x04,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0xff,0x0f,0x1c]
+
+v_mad_mixlo_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0c,0x1c]
+
+v_mad_mixlo_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0xcb,0x0c,0x1c]
+
+v_mad_mixlo_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0xcd,0x0c,0x1c]
+
+v_mad_mixlo_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0xcf,0x0c,0x1c]
+
+v_mad_mixlo_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0xd5,0x0c,0x1c]
+
+v_mad_mixlo_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0xd7,0x0c,0x1c]
+
+v_mad_mixlo_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0xf9,0x0c,0x1c]
+
+v_mad_mixlo_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0xfd,0x0c,0x1c]
+
+v_mad_mixlo_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0xff,0x0c,0x1c]
+
+v_mad_mixlo_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0xfe,0x1f]
+
+v_mad_mixlo_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x18]
+
+v_mad_mixlo_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x96,0x19]
+
+v_mad_mixlo_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x9a,0x19]
+
+v_mad_mixlo_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x9e,0x19]
+
+v_mad_mixlo_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0xaa,0x19]
+
+v_mad_mixlo_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0xae,0x19]
+
+v_mad_mixlo_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0xf2,0x19]
+
+v_mad_mixlo_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0xfa,0x19]
+
+v_mad_mixlo_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0xfe,0x19]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,0,0]
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[1,0,0]
+// CHECK: [0x05,0x48,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,1,0]
+// CHECK: [0x05,0x50,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,0,1]
+// CHECK: [0x05,0x60,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[1,1,1]
+// CHECK: [0x05,0x78,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1]
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,0,0]
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0]
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x0c]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0]
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x14]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1]
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x3c]
+
+v_mad_mixlo_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x5c]
+
+v_mad_mixlo_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x9c]
+
+v_mad_mixlo_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0xfc]
+
+v_mad_mixlo_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x41,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x42,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x44,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x47,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0xc0,0xa1,0xd3,0x01,0x05,0x0e,0x1c]

llvm/trunk/test/MC/AMDGPU/vop3p-err.s

 v_pk_add_f16 v1, v2, -v3
 
 // GFX9: :21: error: not a valid operand.
 v_pk_add_u16 v1, abs(v2), v3
 
 // GFX9: :19: error: invalid operand for instruction
 v_pk_add_u16 v1, -v2, v3
 
-
-//
-// Packed operands on the non-packed VOP3P instructions
-//
-
-// GFX9: invalid operand for instruction
-v_mad_mix_f32 v1, v2, v3, v4 op_sel:[0,0,0]
-
-// GFX9: invalid operand for instruction
-v_mad_mix_f32 v1, v2, v3, v4 op_sel_hi:[0,0,0]
-
-// GFX9: invalid operand for instruction
-v_mad_mix_f32 v1, v2, v3, v4 neg_lo:[0,0,0]
-
-// GFX9: invalid operand for instruction
-v_mad_mix_f32 v1, v2, v3, v4 neg_hi:[0,0,0]
-
-// GFX9: invalid operand for instruction
-v_mad_mixlo_f16 v1, v2, v3, v4 op_sel:[0,0,0]
-
-// GFX9: invalid operand for instruction
-v_mad_mixlo_f16 v1, v2, v3, v4 op_sel_hi:[0,0,0]
-
-// GFX9: invalid operand for instruction
-v_mad_mixlo_f16 v1, v2, v3, v4 neg_lo:[0,0,0]
-
-// GFX9: invalid operand for instruction
-v_mad_mixlo_f16 v1, v2, v3, v4 neg_hi:[0,0,0]
-
-// GFX9: invalid operand for instruction
-v_mad_mixhi_f16 v1, v2, v3, v4 op_sel:[0,0,0]
-
-// GFX9: invalid operand for instruction
-v_mad_mixhi_f16 v1, v2, v3, v4 op_sel_hi:[0,0,0]
-
-// GFX9: invalid operand for instruction
-v_mad_mixhi_f16 v1, v2, v3, v4 neg_lo:[0,0,0]
-
-// GFX9: invalid operand for instruction
-v_mad_mixhi_f16 v1, v2, v3, v4 neg_hi:[0,0,0]
-
 //
 // Constant bus restrictions
 //
 
 // GFX9: invalid operand (violates constant bus restrictions)
 v_pk_add_f16 v255, s1, s2

llvm/trunk/test/MC/AMDGPU/vop3p.s

 
 v_pk_min_f16 v0, v1, v2
 // GFX9: v_pk_min_f16 v0, v1, v2 ; encoding: [0x00,0x00,0x91,0xd3,0x01,0x05,0x02,0x18]
 
 v_pk_max_f16 v0, v1, v2
 // GFX9: v_pk_max_f16 v0, v1, v2 ; encoding: [0x00,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
 
 v_mad_mix_f32 v0, v1, v2, v3
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
 
 v_mad_mixlo_f16 v0, v1, v2, v3
-// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 ; encoding: [0x00,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
 
 v_mad_mixhi_f16 v0, v1, v2, v3
-// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
+// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 ; encoding: [0x00,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
 
 //
 // Regular source modifiers on non-packed instructions
 //
 
 v_mad_mix_f32 v0, abs(v1), v2, v3
-// GFX9: v_mad_mix_f32 v0, |v1|, v2, v3 ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, |v1|, v2, v3  ; encoding: [0x00,0x41,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
 
 v_mad_mix_f32 v0, v1, abs(v2), v3
-// GFX9: v_mad_mix_f32 v0, v1, |v2|, v3 ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, |v2|, v3  ; encoding: [0x00,0x42,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
 
 v_mad_mix_f32 v0, v1, v2, abs(v3)
-// GFX9: v_mad_mix_f32 v0, v1, v2, |v3| ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, |v3|  ; encoding: [0x00,0x44,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
 
 v_mad_mix_f32 v0, -v1, v2, v3
-// GFX9: v_mad_mix_f32 v0, -v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]
+// GFX9: v_mad_mix_f32 v0, -v1, v2, v3   ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x3c]
 
 v_mad_mix_f32 v0, v1, -v2, v3
-// GFX9: v_mad_mix_f32 v0, v1, -v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]
+// GFX9: v_mad_mix_f32 v0, v1, -v2, v3   ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x5c]
 
 v_mad_mix_f32 v0, v1, v2, -v3
-// GFX9: v_mad_mix_f32 v0, v1, v2, -v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]
+// GFX9: v_mad_mix_f32 v0, v1, v2, -v3   ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x9c]
 
 v_mad_mix_f32 v0, -abs(v1), v2, v3
-// GFX9: v_mad_mix_f32 v0, -|v1|, v2, v3 ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x24]
+// GFX9: v_mad_mix_f32 v0, -|v1|, v2, v3 ; encoding: [0x00,0x41,0xa0,0xd3,0x01,0x05,0x0e,0x3c]
 
 v_mad_mix_f32 v0, v1, -abs(v2), v3
-// GFX9: v_mad_mix_f32 v0, v1, -|v2|, v3 ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x44]
+// GFX9: v_mad_mix_f32 v0, v1, -|v2|, v3 ; encoding: [0x00,0x42,0xa0,0xd3,0x01,0x05,0x0e,0x5c]
 
 v_mad_mix_f32 v0, v1, v2, -abs(v3)
-// GFX9: v_mad_mix_f32 v0, v1, v2, -|v3| ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x84]
+// GFX9: v_mad_mix_f32 v0, v1, v2, -|v3| ; encoding: [0x00,0x44,0xa0,0xd3,0x01,0x05,0x0e,0x9c]
 
 v_mad_mixlo_f16 v0, abs(v1), -v2, abs(v3)
-// GFX9: v_mad_mixlo_f16 v0, |v1|, -v2, |v3| ; encoding: [0x00,0x05,0xa1,0xd3,0x01,0x05,0x0e,0x44]
+// GFX9: v_mad_mixlo_f16 v0, |v1|, -v2, |v3| ; encoding: [0x00,0x45,0xa1,0xd3,0x01,0x05,0x0e,0x5c]
 
 v_mad_mixhi_f16 v0, -v1, abs(v2), -abs(v3)
-// GFX9: v_mad_mixhi_f16 v0, -v1, |v2|, -|v3| ; encoding: [0x00,0x06,0xa2,0xd3,0x01,0x05,0x0e,0xa4]
+// GFX9: v_mad_mixhi_f16 v0, -v1, |v2|, -|v3| ; encoding: [0x00,0x46,0xa2,0xd3,0x01,0x05,0x0e,0xbc]
+
+//
+// op_sel with non-packed instructions
+//
+
+v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,0]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3    ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x00,0x48,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x00,0x50,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x00,0x60,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x00,0x78,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,0,0]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c]
+
+v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,1,0]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14]
+
+v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,1]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,1] ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,1,1]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3    ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]