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[PowerPC] fix latency for simple integer instructions in POWER9 scheduler
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Authored by inouehrs on Jun 29 2017, 11:48 PM.

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Summary

In the POWER9 instruction scheduler, SchedWriteRes for the simple integer instructions are misconfigured to use that of (costly) DFU instructions.
This results in surprisingly long instruction latency estimation and causes misbehavior in some optimizers such as if-conversion.

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Repository
rL LLVM

Event Timeline

inouehrs created this revision.Jun 29 2017, 11:48 PM
nemanjai accepted this revision.Jul 10 2017, 10:10 PM

There are more changes coming to the scheduler but since this is up on Phabricator already, please go ahead and commit this. Of course, if this changes the behaviour of any test cases that are sensitive to P9 scheduling, please update them.

This revision is now accepted and ready to land.Jul 10 2017, 10:10 PM
This revision was automatically updated to reflect the committed changes.

I tested with the latest code base again, but no test case was affected by this change.