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Allow GHC calling convention to use YMM and ZMM registers
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Authored by bgamari on Jun 29 2017, 5:55 PM.

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Reviewers

RKSimon
craig.topper

Commits

rG4050c77d33a6: [X86] Allow GHC calling convention to use YMM and ZMM registers
rL307504: [X86] Allow GHC calling convention to use YMM and ZMM registers

Summary

GHC 8.4 will know how to use YMM and ZMM registers for calls.

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Repository: rL LLVM

Event Timeline

bgamari created this revision.Jun 29 2017, 5:55 PM

Adding @pcc as a reviewer for lack of a better idea. Feel free to suggest someone else @pcc.

Simon should probably review this change.

RKSimon added a reviewer: craig.topper.Jul 1 2017, 4:35 AM

LGTM

This revision is now accepted and ready to land.Jul 4 2017, 10:52 AM

In D34854#799059, @RKSimon wrote:

LGTM

Can someone merge this? I'm afraid I don't have commit bits.

And, of course, thanks for your help!

Closed by commit rL307504: [X86] Allow GHC calling convention to use YMM and ZMM registers (authored by RKSimon). · Explain WhyJul 9 2017, 9:57 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents

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llvm/

trunk/

lib/

Target/

X86/

X86CallingConv.td

10 lines

Diff 105783

llvm/trunk/lib/Target/X86/X86CallingConv.td

Show First 20 Lines • Show All 645 Lines • ▼ Show 20 Lines	def CC_X86_64_GHC : CallingConv<[

// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim		// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
CCIfType<[i64],		CCIfType<[i64],
CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,		CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,

// Pass in STG registers: F1, F2, F3, F4, D1, D2		// Pass in STG registers: F1, F2, F3, F4, D1, D2
CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],		CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
CCIfSubtarget<"hasSSE1()",		CCIfSubtarget<"hasSSE1()",
CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>		CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>,
		// AVX
		CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
		CCIfSubtarget<"hasAVX()",
		CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>,
		// AVX-512
		CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
		CCIfSubtarget<"hasAVX512()",
		CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>>
]>;		]>;

def CC_X86_64_HiPE : CallingConv<[		def CC_X86_64_HiPE : CallingConv<[
// Promote i8/i16/i32 arguments to i64.		// Promote i8/i16/i32 arguments to i64.
CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,		CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,

// Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3		// Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,		CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
▲ Show 20 Lines • Show All 463 Lines • Show Last 20 Lines