[X86] Add RDRND to Goldmont. Add MOVBE to all Atom CPUs

[craig.topper]

Summary

This adds to RDNRND to Goldmont as I believe it has that feature in addition to RDSEED.

I don't know how to test the MOVBE part since we don't have a MOVBE macro nor do we need one. The backend will already infer the feature from the CPU name. We do have a command line switch to force it on and off regardless of CPU. So really I don't even think this change is necessary, I just found it inconsistent that the movbe handling existed for the command line option, but was not bound to any CPU.

[RKSimon]

LGTM with a couple of comments.

On the LLVM side, X86.td GoldMont class looks like it needs RDRAND as well.

lib/Basic/Targets.cpp

3310

Is it worth doing the reordering first as an NFC? Then add MOVBE?

[craig.topper]

There's a separate review for X86.d https://reviews.llvm.org/D34828

lib/Basic/Targets.cpp

bool X86TargetInfo::initFeatureMap(
   case CK_Yonah:
   case CK_Prescott:
   case CK_Nocona:
     setFeatureEnabledImpl(Features, "sse3", true);
     setFeatureEnabledImpl(Features, "fxsr", true);
     setFeatureEnabledImpl(Features, "cx16", true);
     break;
   case CK_Core2:
-  case CK_Bonnell:
     setFeatureEnabledImpl(Features, "ssse3", true);
     setFeatureEnabledImpl(Features, "fxsr", true);
     setFeatureEnabledImpl(Features, "cx16", true);
     break;
   case CK_Penryn:
     setFeatureEnabledImpl(Features, "sse4.1", true);
     setFeatureEnabledImpl(Features, "fxsr", true);
     setFeatureEnabledImpl(Features, "cx16", true);
case CK_IvyBridge:
     setFeatureEnabledImpl(Features, "fsgsbase", true);
     LLVM_FALLTHROUGH;
   case CK_SandyBridge:
     setFeatureEnabledImpl(Features, "avx", true);
     setFeatureEnabledImpl(Features, "xsave", true);
     setFeatureEnabledImpl(Features, "xsaveopt", true);
     LLVM_FALLTHROUGH;
   case CK_Westmere:
-  case CK_Silvermont:
     setFeatureEnabledImpl(Features, "aes", true);
     setFeatureEnabledImpl(Features, "pclmul", true);
     LLVM_FALLTHROUGH;
   case CK_Nehalem:
     setFeatureEnabledImpl(Features, "sse4.2", true);
     setFeatureEnabledImpl(Features, "fxsr", true);
     setFeatureEnabledImpl(Features, "cx16", true);
     break;
   case CK_Goldmont:
     setFeatureEnabledImpl(Features, "sha", true);
+    setFeatureEnabledImpl(Features, "rdrnd", true);
     setFeatureEnabledImpl(Features, "rdseed", true);
     setFeatureEnabledImpl(Features, "xsave", true);
     setFeatureEnabledImpl(Features, "xsaveopt", true);
     setFeatureEnabledImpl(Features, "xsavec", true);
     setFeatureEnabledImpl(Features, "xsaves", true);
     setFeatureEnabledImpl(Features, "clflushopt", true);
     setFeatureEnabledImpl(Features, "mpx", true);
+    LLVM_FALLTHROUGH;
+  case CK_Silvermont:
     setFeatureEnabledImpl(Features, "aes", true);
     setFeatureEnabledImpl(Features, "pclmul", true);
     setFeatureEnabledImpl(Features, "sse4.2", true);
+    LLVM_FALLTHROUGH;
+  case CK_Bonnell:
+    setFeatureEnabledImpl(Features, "ssse3", true);
+    setFeatureEnabledImpl(Features, "movbe", true);
     setFeatureEnabledImpl(Features, "fxsr", true);
     setFeatureEnabledImpl(Features, "cx16", true);
     break;
   case CK_KNL:
     setFeatureEnabledImpl(Features, "avx512f", true);
     setFeatureEnabledImpl(Features, "avx512cd", true);
     setFeatureEnabledImpl(Features, "avx512er", true);
     setFeatureEnabledImpl(Features, "avx512pf", true);
     setFeatureEnabledImpl(Features, "prefetchwt1", true);
     setFeatureEnabledImpl(Features, "fxsr", true);
     setFeatureEnabledImpl(Features, "rdseed", true);

test/Preprocessor/predefined-arch-macros.c

 // RUN:   | FileCheck %s -check-prefix=CHECK_GLM_M32
 // CHECK_GLM_M32: #define __AES__ 1
 // CHECK_GLM_M32: #define __CLFLUSHOPT__ 1
 // CHECK_GLM_M32: #define __FXSR__ 1
 // CHECK_GLM_M32: #define __MMX__ 1
 // CHECK_GLM_M32: #define __MPX__ 1
 // CHECK_GLM_M32: #define __PCLMUL__ 1
 // CHECK_GLM_M32: #define __POPCNT__ 1
+// CHECK_GLM_M32: #define __RDRND__ 1
 // CHECK_GLM_M32: #define __RDSEED__ 1
 // CHECK_GLM_M32: #define __SHA__ 1
 // CHECK_GLM_M32: #define __SSE2__ 1
 // CHECK_GLM_M32: #define __SSE3__ 1
 // CHECK_GLM_M32: #define __SSE4_1__ 1
 // CHECK_GLM_M32: #define __SSE4_2__ 1
 // CHECK_GLM_M32: #define __SSE_MATH__ 1
 // CHECK_GLM_M32: #define __SSE__ 1

 // RUN:   | FileCheck %s -check-prefix=CHECK_GLM_M64
 // CHECK_GLM_M64: #define __AES__ 1
 // CHECK_GLM_M64: #define __CLFLUSHOPT__ 1
 // CHECK_GLM_M64: #define __FXSR__ 1
 // CHECK_GLM_M64: #define __MMX__ 1
 // CHECK_GLM_M64: #define __MPX__ 1
 // CHECK_GLM_M64: #define __PCLMUL__ 1
 // CHECK_GLM_M64: #define __POPCNT__ 1
+// CHECK_GLM_M64: #define __RDRND__ 1
 // CHECK_GLM_M64: #define __RDSEED__ 1
 // CHECK_GLM_M64: #define __SSE2__ 1
 // CHECK_GLM_M64: #define __SSE3__ 1
 // CHECK_GLM_M64: #define __SSE4_1__ 1
 // CHECK_GLM_M64: #define __SSE4_2__ 1
 // CHECK_GLM_M64: #define __SSE__ 1
 // CHECK_GLM_M64: #define __SSSE3__ 1
 // CHECK_GLM_M64: #define __XSAVEC__ 1