[InstCombine] Remove 64-bit bit width restriction from m_ConstantInt(uint64_t*&)

[craig.topper]

Summary

I think we only need to make sure the value fits in 64-bits not that bit width is 64-bit.

This helps places that use this for shift amounts since the shift amount needs to be the same bitwidth as the LHS, but can't be larger than the bit width.

[spatel]

LGTM.

test/Transforms/InstCombine/icmp.ll

765

Update comment.

include/llvm/IR/PatternMatch.h

 
 struct bind_const_intval_ty {
   uint64_t &VR;
 
   bind_const_intval_ty(uint64_t &V) : VR(V) {}
 
   template <typename ITy> bool match(ITy *V) {
     if (const auto *CV = dyn_cast<ConstantInt>(V))
-      if (CV->getBitWidth() <= 64) {
-        return false;
+      if (CV->getValue().ule(UINT64_MAX)) {
         VR = CV->getZExtValue();
         return true;
       }
     return false;
   }
 };
 
 /// \brief Match a specified integer value or vector of all elements of that

test/Transforms/InstCombine/icmp.ll

;
   %tmp2 = lshr i32 %x1, 16
   %tmp3 = trunc i32 %tmp2 to i8
   %cmp15 = icmp eq i8 %tmp3, 76
 
   %A = and i1 %cmp, %cmp15
   ret i1 %A
 }
 
 ; TODO we have a 64-bit or less restriction in the handling for this pattern. We should remove that and do the same thing we do above.
 define i1 @test52b(i128 %x1) {
 ; CHECK-LABEL: @test52b(
-; CHECK-NEXT:    [[CONV:%.*]] = and i128 [[X1:%.*]], 255
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i128 [[CONV]], 127
-; CHECK-NEXT:    [[TMP2:%.*]] = lshr i128 [[X1]], 16
-; CHECK-NEXT:    [[TMP3:%.*]] = trunc i128 [[TMP2]] to i8
-; CHECK-NEXT:    [[CMP15:%.*]] = icmp eq i8 [[TMP3]], 76
-; CHECK-NEXT:    [[A:%.*]] = and i1 [[CMP]], [[CMP15]]
-; CHECK-NEXT:    ret i1 [[A]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i128 [[X1:%.*]], 16711935
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i128 [[TMP1]], 4980863
+; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %conv = and i128 %x1, 255
   %cmp = icmp eq i128 %conv, 127
   %tmp2 = lshr i128 %x1, 16
   %tmp3 = trunc i128 %tmp2 to i8
   %cmp15 = icmp eq i8 %tmp3, 76
 
   %A = and i1 %cmp, %cmp15