[PowerPC] set optimization level in SelectionDAGISel

[inouehrs]

Summary

PowerPC backend does not pass the current optimization level to SelectionDAGISel and so SelectionDAGISel works with the default optimization level regardless of the current optimization level.
This patch makes the PowerPC backend set the optimization level correctly.

[hfinkel]

LGTM.

Please make sure that you run a self-hosting test at both -O3 and -O0 (Release and Debug) before committing.

[inouehrs]

committed after bootstrap tests with -O0 and -O3

lib/Target/PowerPC/PPC.h

 // This file contains the entry points for global functions defined in the LLVM
 // PowerPC back-end.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_POWERPC_PPC_H
 #define LLVM_LIB_TARGET_POWERPC_PPC_H
 
+#include "llvm/Support/CodeGen.h"
 #include "MCTargetDesc/PPCMCTargetDesc.h"
 
 // GCC #defines PPC on Linux but we use it as our namespace name
 #undef PPC
 
 namespace llvm {
   class PPCTargetMachine;
   class PassRegistry;
#endif
   FunctionPass *createPPCTOCRegDepsPass();
   FunctionPass *createPPCEarlyReturnPass();
   FunctionPass *createPPCVSXCopyPass();
   FunctionPass *createPPCVSXFMAMutatePass();
   FunctionPass *createPPCVSXSwapRemovalPass();
   FunctionPass *createPPCMIPeepholePass();
   FunctionPass *createPPCBranchSelectionPass();
   FunctionPass *createPPCQPXLoadSplatPass();
-  FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
+  FunctionPass *createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL);
   FunctionPass *createPPCTLSDynamicCallPass();
   FunctionPass *createPPCBoolRetToIntPass();
   FunctionPass *createPPCExpandISELPass();
   void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                     AsmPrinter &AP, bool isDarwin);
 
   void initializePPCVSXFMAMutatePass(PassRegistry&);
   void initializePPCBoolRetToIntPass(PassRegistry&);

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

namespace {
   ///
   class PPCDAGToDAGISel : public SelectionDAGISel {
     const PPCTargetMachine &TM;
     const PPCSubtarget *PPCSubTarget;
     const PPCTargetLowering *PPCLowering;
     unsigned GlobalBaseReg;
 
   public:
-    explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
-        : SelectionDAGISel(tm), TM(tm) {}
+    explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel)
+        : SelectionDAGISel(tm, OptLevel), TM(tm) {}
 
     bool runOnMachineFunction(MachineFunction &MF) override {
       // Make sure we re-emit a set of the global base reg if necessary
       GlobalBaseReg = 0;
       PPCSubTarget = &MF.getSubtarget<PPCSubtarget>();
       PPCLowering = PPCSubTarget->getTargetLowering();
       SelectionDAGISel::runOnMachineFunction(MF);
 
while (Position != CurDAG->allnodes_begin()) {
     if (Base.getNode()->use_empty())
       CurDAG->RemoveDeadNode(Base.getNode());
   }
 }
 
 /// createPPCISelDag - This pass converts a legalized DAG into a
 /// PowerPC-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
-  return new PPCDAGToDAGISel(TM);
+FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM,
+                                     CodeGenOpt::Level OptLevel) {
+  return new PPCDAGToDAGISel(TM, OptLevel);
 }

lib/Target/PowerPC/PPCTargetMachine.cpp

bool PPCPassConfig::addILPOpts() {
   if (EnableMachineCombinerPass)
     addPass(&MachineCombinerID);
 
   return true;
 }
 
 bool PPCPassConfig::addInstSelector() {
   // Install an instruction selector.
-  addPass(createPPCISelDag(getPPCTargetMachine()));
+  addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
 
 #ifndef NDEBUG
   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
     addPass(createPPCCTRLoopsVerify());
 #endif
 
   addPass(createPPCVSXCopyPass());
   return false;

test/CodeGen/PowerPC/anon_aggr.ll

 equal:
   ret i8* %array_ptr
 unequal:
   ret i8* %ptr
 }
 
 ; CHECK-LABEL: func1:
 ; CHECK: cmpld {{([0-9]+,)?}}4, 5
-; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]]
+; CHECK-DAG: std 3, -[[OFFSET1:[0-9]+]]
 ; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
 ; CHECK: ld 3, -[[OFFSET1]](1)
 ; CHECK: ld 3, -[[OFFSET2]](1)
 
 ; DARWIN32: _func1:
 ; DARWIN32: mr
 ; DARWIN32: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]]
 ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
-; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]]
+; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGB]], r[[REGA]]
 ; DARWIN32: stw r[[REG1]], -[[OFFSET1:[0-9]+]]
 ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
-; DARWIN32: lwz r3, -[[OFFSET1]]
 ; DARWIN32: lwz r3, -[[OFFSET2]]
+; DARWIN32: lwz r3, -[[OFFSET1]]
 
 ; DARWIN64: _func1:
 ; DARWIN64: mr
 ; DARWIN64: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]]
 ; DARWIN64: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
-; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]]
-; DARWIN64: std r[[REG1]], -[[OFFSET1:[0-9]+]]
-; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
+; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGB]], r[[REGA]]
+; DARWIN64: std r[[REG1]], -[[OFFSET2:[0-9]+]]
+; DARWIN64: std r[[REG2]], -[[OFFSET1:[0-9]+]]
 ; DARWIN64: ld r3, -[[OFFSET1]]
 ; DARWIN64: ld r3, -[[OFFSET2]]
 
 
 define i8* @func2({ i64, i8* } %array1, %tarray* byval %array2) {
 entry:
   %array1_ptr = extractvalue {i64, i8* } %array1, 1
   %tmp = getelementptr inbounds %tarray, %tarray* %array2, i32 0, i32 1
   %array2_ptr = load i8*, i8** %tmp
   %cond = icmp eq i8* %array1_ptr, %array2_ptr
   br i1 %cond, label %equal, label %unequal
 equal:
   ret i8* %array1_ptr
 unequal:
   ret i8* %array2_ptr
 }
 ; CHECK-LABEL: func2:
-; CHECK: cmpld {{([0-9]+,)?}}4, 6
+; CHECK-DAG: cmpld {{([0-9]+,)?}}4, 6
 ; CHECK-DAG: std 6, 72(1)
 ; CHECK-DAG: std 5, 64(1)
 ; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]]
-; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]]
+; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
 ; CHECK: ld 3, -[[OFFSET2]](1)
 ; CHECK: ld 3, -[[OFFSET1]](1)
 
 ; DARWIN32-LABEL: _func2
-; DARWIN32-DAG: addi r[[REG8:[0-9]+]], r[[REGSP:[0-9]+]], 36
-; DARWIN32-DAG: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
 ; DARWIN32: mr
+; DARWIN32: addi r[[REG8:[0-9]+]], r[[REGSP:[0-9]+]], 36
 ; DARWIN32: mr r[[REG7:[0-9]+]], r5
+; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
 ; DARWIN32-DAG: cmplw {{(cr[0-9]+,)?}}r5, r[[REG2]]
 ; DARWIN32-DAG: stw r[[REG7]], -[[OFFSET1:[0-9]+]]
 ; DARWIN32-DAG: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
 ; DARWIN32-DAG: lwz r3, -[[OFFSET1]]
 ; DARWIN32-DAG: lwz r3, -[[OFFSET2]]
 
 
 ; DARWIN64: _func2:
-; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1)
 ; DARWIN64: mr
 ; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
+; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1)
 ; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]]
 ; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
 ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
 ; DARWIN64: ld r3, -[[OFFSET1]]
 ; DARWIN64: ld r3, -[[OFFSET2]]
 
 
 define i8* @func3({ i64, i8* }* byval %array1, %tarray* byval %array2) {
 entry:
   %tmp1 = getelementptr inbounds { i64, i8* }, { i64, i8* }* %array1, i32 0, i32 1
   %array1_ptr = load i8*, i8** %tmp1
   %tmp2 = getelementptr inbounds %tarray, %tarray* %array2, i32 0, i32 1
   %array2_ptr = load i8*, i8** %tmp2
   %cond = icmp eq i8* %array1_ptr, %array2_ptr
   br i1 %cond, label %equal, label %unequal
 equal:
   ret i8* %array1_ptr
 unequal:
   ret i8* %array2_ptr
 }
 
 ; CHECK-LABEL: func3:
-; CHECK: cmpld {{([0-9]+,)?}}4, 6
-; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]](1)
-; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]](1)
+; CHECK-DAG: cmpld {{([0-9]+,)?}}3, 4
+; CHECK-DAG: std 3, -[[OFFSET2:[0-9]+]](1)
+; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]](1)
 ; CHECK: ld 3, -[[OFFSET2]](1)
 ; CHECK: ld 3, -[[OFFSET1]](1)
 
 ; DARWIN32-LABEL: _func3:
 ; DARWIN32-DAG: stw r[[REG8:[0-9]+]], 44(r[[REGSP:[0-9]+]])
 ; DARWIN32-DAG: stw r[[REG5:[0-9]+]], 32(r[[REGSP]])
 ; DARWIN32-DAG: addi r[[REG5a:[0-9]+]], r[[REGSP:[0-9]+]], 36
 ; DARWIN32-DAG: addi r[[REG8a:[0-9]+]], r[[REGSP]], 24
 ; DARWIN32-DAG: lwz r[[REG5a:[0-9]+]], 44(r[[REGSP]])
 ; DARWIN32-DAG: lwz r[[REG8a:[0-9]+]], 32(r[[REGSP]])
 ; DARWIN32-DAG: cmplw {{(cr[0-9]+,)?}}r[[REG8a]], r[[REG5a]]
 ; DARWIN32-DAG: stw r[[REG5a]], -[[OFFSET1:[0-9]+]]
 ; DARWIN32-DAG: stw r[[REG8a]], -[[OFFSET2:[0-9]+]]
 ; DARWIN32-DAG: lwz r3, -[[OFFSET1:[0-9]+]]
 ; DARWIN32-DAG: lwz r3, -[[OFFSET2:[0-9]+]]
 
 ; DARWIN64: _func3:
-; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1)
-; DARWIN64: ld r[[REG4:[0-9]+]], 56(r1)
+; DARWIN64-DAG: ld r[[REG3:[0-9]+]], 72(r1)
+; DARWIN64-DAG: ld r[[REG4:[0-9]+]], 56(r1)
 ; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]
-; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
-; DARWIN64: std r[[REG4]], -[[OFFSET2:[0-9]+]]
-; DARWIN64: ld r3, -[[OFFSET2]]
+; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]]
+; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]]
 ; DARWIN64: ld r3, -[[OFFSET1]]
+; DARWIN64: ld r3, -[[OFFSET2]]
 
 
 define i8* @func4(i64 %p1, i64 %p2, i64 %p3, i64 %p4,
                   i64 %p5, i64 %p6, i64 %p7, i64 %p8,
                   { i64, i8* } %array1, %tarray* byval %array2) {
 entry:
   %array1_ptr = extractvalue {i64, i8* } %array1, 1
   %tmp = getelementptr inbounds %tarray, %tarray* %array2, i32 0, i32 1
   %array2_ptr = load i8*, i8** %tmp
   %cond = icmp eq i8* %array1_ptr, %array2_ptr
   br i1 %cond, label %equal, label %unequal
 equal:
   ret i8* %array1_ptr
 unequal:
   ret i8* %array2_ptr
 }
 
 ; CHECK-LABEL: func4:
-; CHECK: ld [[REG3:[0-9]+]], 136(1)
-; CHECK: ld [[REG2:[0-9]+]], 120(1)
-; CHECK: cmpld {{([0-9]+,)?}}[[REG2]], [[REG3]]
-; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1)
+; CHECK-DAG: ld [[REG2:[0-9]+]], 120(1)
+; CHECK-DAG: ld [[REG3:[0-9]+]], 136(1)
+; CHECK-DAG: cmpld {{([0-9]+,)?}}[[REG2]], [[REG3]]
 ; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1)
+; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1)
 ; CHECK: ld 3, -[[OFFSET1]](1)
 ; CHECK: ld 3, -[[OFFSET2]](1)
 
 ; DARWIN32: _func4:
 ; DARWIN32: lwz r[[REG4:[0-9]+]], 96(r1)
 ; DARWIN32: addi r[[REG1:[0-9]+]], r1, 100
-; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1)
 ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REG4]]
+; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1)
 ; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]
-; DARWIN32: stw r[[REG2]], -[[OFFSET1:[0-9]+]]
-; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]]
-; DARWIN32: lwz r[[REG1]], -[[OFFSET1]]
-; DARWIN32: lwz r[[REG1]], -[[OFFSET2]]
+; DARWIN32-DAG: stw r[[REG2]], -[[OFFSET1:[0-9]+]]
+; DARWIN32-DAG: stw r[[REG3]], -[[OFFSET2:[0-9]+]]
+; DARWIN32: lwz r3, -[[OFFSET1]]
+; DARWIN32: lwz r3, -[[OFFSET2]]
 
 ; DARWIN64: _func4:
 ; DARWIN64: ld r[[REG2:[0-9]+]], 120(r1)
-; DARWIN64: ld r[[REG3:[0-9]+]], 136(r1)
-; DARWIN64: mr r[[REG4:[0-9]+]], r[[REG2]]
+; DARWIN64-DAG: ld r[[REG3:[0-9]+]], 136(r1)
+; DARWIN64-DAG: mr r[[REG4:[0-9]+]], r[[REG2]]
 ; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG2]], r[[REG3]]
-; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]]
 ; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]]
+; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]]
 ; DARWIN64: ld r3, -[[OFFSET1]]
 ; DARWIN64: ld r3, -[[OFFSET2]]

test/CodeGen/PowerPC/floatPSA.ll

-; RUN: llc -verify-machineinstrs -O0 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -O2 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
 
 ; This verifies that single-precision floating point values that can't
 ; be passed in registers are stored in the rightmost word of the parameter
 ; save area slot.  There are 13 architected floating-point registers, so
 ; the 14th is passed in storage.  The address of the 14th argument is
 ; 48 (fixed size of the linkage area) + 13 * 8 (first 13 args) + 4
 ; (offset to second word) = 156.
 

test/CodeGen/PowerPC/ppc64-align-long-double.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false -mattr=-vsx < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-P9 %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -fast-isel=false -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-P9 %s
 
 ; Verify internal alignment of long double in a struct.  The double
 ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
 ; the long double.  Check that these are stored to proper locations
 ; in the parameter save area and loaded from there for return in FPR1/2.
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"

 ; FIXMECHECK: lfd 2, 72(1)
 
 ; CHECK-VSX-DAG: std 6, 72(1)
 ; CHECK-VSX-DAG: std 5, 64(1)
 ; CHECK-VSX-DAG: std 4, 56(1)
 ; CHECK-VSX-DAG: std 3, 48(1)
 ; CHECK-VSX-DAG: std 5, -16(1)
 ; CHECK-VSX-DAG: std 6, -8(1)
-; CHECK-VSX: addi 3, 1, -16
-; CHECK-VSX: lxsdx 1, 0, 3
-; CHECK-VSX: addi 3, 1, -8
+; CHECK-VSX-DAG: addi [[REG1:[0-9]+]], 1, -16
+; CHECK-VSX-DAG: addi 3, 1, -8
+; CHECK-VSX: lxsdx 1, 0, [[REG1]]
 ; CHECK-VSX: lxsdx 2, 0, 3
 
 ; FIXME-VSX: addi 4, 1, 48
 ; FIXME-VSX: lxsdx 1, 4, 3
 ; FIXME-VSX: li 3, 24
 ; FIXME-VSX: lxsdx 2, 4, 3
 
-; CHECK-P9: std 6, 72(1)
-; CHECK-P9: std 5, 64(1)
-; CHECK-P9: std 4, 56(1)
-; CHECK-P9: std 3, 48(1)
-; CHECK-P9: mtvsrd 1, 5
-; CHECK-P9: mtvsrd 2, 6
+; CHECK-P9-DAG: std 6, 72(1)
+; CHECK-P9-DAG: std 5, 64(1)
+; CHECK-P9-DAG: std 4, 56(1)
+; CHECK-P9-DAG: std 3, 48(1)
+; CHECK-P9-DAG: mtvsrd 1, 5
+; CHECK-P9-DAG: mtvsrd 2, 6

test/CodeGen/PowerPC/tls.ll

 ; RUN: llc -relocation-model=static -verify-machineinstrs -O0 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s
 ; RUN: llc -relocation-model=static -verify-machineinstrs -O1 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s
 ; RUN: llc -verify-machineinstrs -O0 < %s -march=ppc32 -mcpu=ppc | FileCheck -check-prefix=OPT0-PPC32 %s
 
 target triple = "powerpc64-unknown-linux-gnu"
 
 @a = thread_local global i32 0, align 4
 
 ;OPT0-LABEL:          localexec:
 ;OPT1-LABEL:          localexec:
 define i32 @localexec() nounwind {
 entry:
 ;OPT0:          addis [[REG1:[0-9]+]], 13, a@tprel@ha
-;OPT0-NEXT:     li [[REG2:[0-9]+]], 42
 ;OPT0-NEXT:     addi [[REG1]], [[REG1]], a@tprel@l
+;OPT0-NEXT:     li [[REG2:[0-9]+]], 42
 ;OPT0:          stw [[REG2]], 0([[REG1]])
 ;OPT1:          addis [[REG1:[0-9]+]], 13, a@tprel@ha
 ;OPT1-NEXT:     li [[REG2:[0-9]+]], 42
 ;OPT1-NEXT:     stw [[REG2]], a@tprel@l([[REG1]])
   store i32 42, i32* @a, align 4
   ret i32 0
 }