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Differential D34379

AMDGPU: Preserve undef when folding register operands
ClosedPublic

Authored by arsenm on Jun 19 2017, 7:24 PM.

Details

Reviewers
rampitec
Summary

If the source was a copy of an undef register, this would
produce a read of an undefined register which is a verifier
error.

Diff Detail
Event Timeline
arsenm created this revision.Jun 19 2017, 7:24 PM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others.  ·  View Herald TranscriptJun 19 2017, 7:24 PM
rampitec accepted this revision.Jun 19 2017, 7:27 PM
LGTM
This revision is now accepted and ready to land.Jun 19 2017, 7:27 PM
arsenm closed this revision.Jun 20 2017, 11:42 AM
r305816
Revision Contents
PathSize
lib/
Target/
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
6 lines
Diff 103139
lib/Target/AMDGPU/SIFoldOperands.cpp
Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Lines  if (Fold.isFI()) {

    Old.ChangeToFrameIndex(Fold.FrameIndexToFold);
    Old.ChangeToFrameIndex(Fold.FrameIndexToFold);

    return true;
    return true;

  }
  }




  MachineOperand *New = Fold.OpToFold;
  MachineOperand *New = Fold.OpToFold;

  if (TargetRegisterInfo::isVirtualRegister(Old.getReg()) &&
  if (TargetRegisterInfo::isVirtualRegister(Old.getReg()) &&

      TargetRegisterInfo::isVirtualRegister(New->getReg())) {
      TargetRegisterInfo::isVirtualRegister(New->getReg())) {

    Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
    Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);



    Old.setIsUndef(New->isUndef());

    return true;
    return true;

  }
  }




  // FIXME: Handle physical registers.
  // FIXME: Handle physical registers.




  return false;
  return false;

}
}




▲ Show 20 Lines • Show All 791 Lines • Show Last 20 Lines
test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
Show First 20 Lines • Show All 858 Lines • ▼ Show 20 Lines  bb.0 (%ir-block.0):




    S_ENDPGM
    S_ENDPGM




...
...

---
---

# There is only an undef use operand for %1, so there is no
# There is only an undef use operand for %1, so there is no

# corresponding defining instruction
# corresponding defining instruction




# GCN-LABEL: name: undefined_vreg_operand{{$}}

# GCN: bb.0

# GCN-NEXT: FLAT_STORE_DWORD undef %3, undef %1,

# GCN-NEXT: S_ENDPGM

name: undefined_vreg_operand
name: undefined_vreg_operand

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: vgpr_32, preferred-register: '' }
  - { id: 0, class: vgpr_32, preferred-register: '' }

  - { id: 1, class: vgpr_32, preferred-register: '' }
  - { id: 1, class: vgpr_32, preferred-register: '' }

  - { id: 2, class: vgpr_32, preferred-register: '' }
  - { id: 2, class: vgpr_32, preferred-register: '' }

  - { id: 3, class: vreg_64, preferred-register: '' }

body:             |
body:             |

  bb.0:
  bb.0:

    %0 = V_MOV_B32_e32 0, implicit %exec
    %0 = V_MOV_B32_e32 0, implicit %exec

    %2 = V_XOR_B32_e64 killed %0, undef %1, implicit %exec
    %2 = V_XOR_B32_e64 killed %0, undef %1, implicit %exec

    FLAT_STORE_DWORD undef %3, %2, 0, 0, 0, implicit %exec, implicit %flat_scr

    S_ENDPGM
    S_ENDPGM




...
...