AMDGPU: Fix crash with undef vreg input operand

[rampitec]

lib/Target/AMDGPU/SIFoldOperands.cpp

472

getUniqueVRegDef?

[arsenm]

lib/Target/AMDGPU/SIFoldOperands.cpp

472

I think that should only ever be used post-SSA. This is an SSA pass, so the concern isn't whether or not there are multiple defs of the same register

[rampitec]

lib/Target/AMDGPU/SIFoldOperands.cpp

472

If works fine past SSA in general, so I believe it is better to fix that as well.

[arsenm]

lib/Target/AMDGPU/SIFoldOperands.cpp

472

I'm not sure what you mean. I don't think it works post-SSA. Changing that belongs as a separate change if that ends up being useful

[rampitec]

OK, let's agree on a separate change when needed.

[arsenm]

r305814

lib/Target/AMDGPU/SIFoldOperands.cpp

 
 static MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI,
                                                MachineOperand &Op) {
   if (Op.isReg()) {
     // If this has a subregister, it obviously is a register source.
     if (Op.getSubReg() != AMDGPU::NoSubRegister)
       return &Op;
 
     MachineInstr *Def = MRI.getVRegDef(Op.getReg());
-    if (Def->isMoveImmediate()) {
+    if (Def && Def->isMoveImmediate()) {
       MachineOperand &ImmSrc = Def->getOperand(1);
       if (ImmSrc.isImm())
         return &ImmSrc;
     }
   }
 
   return &Op;
 }

test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir

define amdgpu_kernel void @v_fold_lshr_imm_regimm_32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #0 {
     %gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i64 %idxprom
     %gep.out = getelementptr i32, i32 addrspace(1)* %out, i64 %idxprom
     %a = load i32, i32 addrspace(1)* %gep.a
     %lshr = lshr i32 %a, 12
     store i32 %lshr, i32 addrspace(1)* %gep.out
     ret void
   }
 
+  define amdgpu_kernel void @undefined_vreg_operand() {
+    unreachable
+  }
+
   declare i32 @llvm.amdgcn.workitem.id.x() #1
 
   attributes #0 = { nounwind }
   attributes #1 = { nounwind readnone }
 
 ...
 ---
 
bb.0 (%ir-block.0):
     FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
 
     %28 = V_LSHR_B32_e32 %27, %35, implicit %exec
     FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
 
     S_ENDPGM
 
 ...
+---
+# There is only an undef use operand for %1, so there is no
+# corresponding defining instruction
+
+name: undefined_vreg_operand
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '' }
+  - { id: 1, class: vgpr_32, preferred-register: '' }
+  - { id: 2, class: vgpr_32, preferred-register: '' }
+body:             |
+  bb.0:
+    %0 = V_MOV_B32_e32 0, implicit %exec
+    %2 = V_XOR_B32_e64 killed %0, undef %1, implicit %exec
+    S_ENDPGM
+
+...