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[mips] Alter register classes for MSA pseudo f16 instructions
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Authored by smaksimovic on Jun 16 2017, 6:31 AM.

Details

Summary

This change introduces additional machine instructions in functions dealing with the expansion of
msa pseudo f16 instructions due to register classes being inappropriate when checked with machine verifier.

Diff Detail

Event Timeline

smaksimovic created this revision.Jun 16 2017, 6:31 AM
sdardis requested changes to this revision.Jun 21 2017, 6:28 AM

The conversions introduced by this patch are incorrect. fexdo.[hw] and fexupr.[wd] implement the necessary down and up scaling of a floating point value.

The other nit I see if that you're creating virtual registers unconditionally, ideally they should only be created when they are going to be used.

lib/Target/Mips/MipsSEISelLowering.cpp
3420–3428

Rather than unconditionally allocating a virtual GPR64 register, you should instead have the output of COPY_U_H go to Rs, then if !UsingMips32, allocate a GPR64 and perform the SUBREG_TO_REG to writing the temp register, then assign the value of the temp register to Rs.

Then you don't need the conditional on line 3606.

3477–3479

You can sink the creation of the virtual register into the if block, along with "Rt = Tmp;" after emitting the copy.

3569–3570

This is incorrect as it's inconsistent with the logic below.

If the input is a FPR64 on Mips32, this patch changes the expansion to convert a double precision value to a single precision value. This value is then written to all the word lanes.

Lines 3749 - 3763 will write the upper 32bits of the original double into the odd lanes which result in incorrect values in the register when we perform FEXDO_W as that instruction expects doubles in the vector register.

3695–3697

This is incorrect, the input to the conversion is not single precision value, and it's been overwritten by the MTHC1.

This revision now requires changes to proceed.Jun 21 2017, 6:28 AM

To follow up my previous comments, those conversions should be copies to or from sub-registers.

smaksimovic edited edge metadata.
  • Moved virtual registers inside if blocks
  • Introduced mtc1/mfc1 counterparts which use FGR64Opnd since copies between FGR32 and FGR64 register classes cannot be performed
sdardis accepted this revision.Jul 14 2017, 7:49 AM

LGTM.

This revision is now accepted and ready to land.Jul 14 2017, 7:49 AM
This revision was automatically updated to reflect the committed changes.