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Differential D34048

[PowerPC] Eliminate compares - add i32 sext/zext handling for SETLE/SETGE
ClosedPublic

Authored by nemanjai on Jun 9 2017, 12:15 AM.

Details

Reviewers
echristo
hfinkel
kbarton
Commits
rGfe6b509f834d: [PowerPC] Revert r310346 (and followups r310356 & r310424) which introduce a…
rG809fbfa6a16e: [PowerPC] Eliminate compares - add i32 sext/zext handling for SETLE/SETGE
rL310809: [PowerPC] Revert r310346 (and followups r310356 & r310424) which
rL310346: [PowerPC] Eliminate compares - add i32 sext/zext handling for SETLE/SETGE
Summary

This patch adds a bit more of the infrastructure for doing comparisons in GPR's. It provides GE/LE patterns for i32's as well as the computation for GE/LE comparisons against zero for both i32 and i64.

Posting this for review since it's not just a patch that adds patterns - there's a bit of additional infrastructure.

Diff Detail

Repository
rL LLVM

Event Timeline

nemanjai created this revision.Jun 9 2017, 12:15 AM
nemanjai added inline comments.
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
2861

OK, I realize this shouldn't have been handled "above above". The commit will have just one "above". :)

nemanjai added inline comments.Jun 13 2017, 5:17 AM
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
2809

I realize that the three by-ref bool's makes this signature look kind of busy. Perhaps it would be better to just encode these as bits in a single char or something along those lines?

echristo added inline comments.Jun 15 2017, 6:58 PM
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
2809

You don't appear to use the values anywhere after they're set or am I missing something?

nemanjai marked an inline comment as done.Aug 2 2017, 3:20 AM
nemanjai added inline comments.
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
2809

The values are used after LLVM_FALLTHROUGH. For example line 2937, etc.

nemanjai updated this revision to Diff 109313.Aug 2 2017, 3:27 AM

Rebased and fixed the assert message.

nemanjai added inline comments.Aug 2 2017, 3:31 AM
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
2879

IsRHSOne/IsRHSNegOne are not currently used but will be used to produce the LHS <= 0 sequence for LHS < 1 and the LHS >= 0 sequence for LHS > -1 in a subsequent patch.

Rather than omitting them from this patch and the function that re-sets them, I left them in. This way if this isn't how we want to implement swapAndReset(), I can address it in this patch rather than having to re-work it in the next.

echristo added inline comments.Aug 2 2017, 1:41 PM
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
2879

I don't like committing dead code so let's try to avoid that.

The swapAndReset function is a little unusual. I'd probably just suggest grabbing the values you need as you need them rather than breaking it out into a function. Depending on how it looks I'd just comment the swap and fall through.

Thoughts?

nemanjai added inline comments.Aug 2 2017, 2:06 PM
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
2879

Actually, I think that makes sense. At every place where we'd call that function, we just need to swap and set one of the three Boolean variables. I'll get rid of the function and put the code in the caller.

nemanjai updated this revision to Diff 109543.Aug 3 2017, 6:46 AM

Remove the odd swapAndReset() function.

echristo accepted this revision.Aug 3 2017, 1:29 PM

One inline comment, otherwise lgtm.

-eric

lib/Target/PowerPC/PPCISelDAGToDAG.cpp
2913

Comment on these that we're going to swap and fallthrough?

This revision is now accepted and ready to land.Aug 3 2017, 1:29 PM
Closed by commit rL310346: [PowerPC] Eliminate compares - add i32 sext/zext handling for SETLE/SETGE (authored by nemanjai). · Explain WhyAug 8 2017, 4:21 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 109543

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Show First 20 Lines • Show All 276 Lines • ▼ Show 20 Linesprivate:
// Modifiers to guide how an ISD::SETCC node's result is to be computed // Modifiers to guide how an ISD::SETCC node's result is to be computed
// in a GPR. // in a GPR.
// ZExtOrig - use the original condition code, zero-extend value // ZExtOrig - use the original condition code, zero-extend value
// ZExtInvert - invert the condition code, zero-extend value // ZExtInvert - invert the condition code, zero-extend value
// SExtOrig - use the original condition code, sign-extend value // SExtOrig - use the original condition code, sign-extend value
// SExtInvert - invert the condition code, sign-extend value // SExtInvert - invert the condition code, sign-extend value
enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert }; enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert };
// Comparisons against zero to emit GPR code sequences for. Each of these
// sequences may need to be emitted for two or more equivalent patterns.
// For example (a >= 0) == (a > -1).
enum ZeroCompare { GEZExt, GESExt, LEZExt, LESExt };
bool trySETCC(SDNode *N); bool trySETCC(SDNode *N);
bool tryEXTEND(SDNode *N); bool tryEXTEND(SDNode *N);
bool tryLogicOpOfCompares(SDNode *N); bool tryLogicOpOfCompares(SDNode *N);
SDValue computeLogicOpInGPR(SDValue LogicOp); SDValue computeLogicOpInGPR(SDValue LogicOp);
SDValue signExtendInputIfNeeded(SDValue Input); SDValue signExtendInputIfNeeded(SDValue Input);
SDValue zeroExtendInputIfNeeded(SDValue Input); SDValue zeroExtendInputIfNeeded(SDValue Input);
SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv); SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv);
SDValue getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
ZeroCompare CmpTy);
SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl); int64_t RHSValue, SDLoc dl);
SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl); int64_t RHSValue, SDLoc dl);
SDValue get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl); int64_t RHSValue, SDLoc dl);
SDValue get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl); int64_t RHSValue, SDLoc dl);
▲ Show 20 Lines • Show All 2,492 Lines • ▼ Show 20 LinesSDValue PPCDAGToDAGISel::addExtOrTrunc(SDValue NatWidthRes,
// For reinterpreting 64-bit values as 32-bit values, we just need to // For reinterpreting 64-bit values as 32-bit values, we just need to
// EXTRACT_SUBREG (i.e. extract the low word). // EXTRACT_SUBREG (i.e. extract the low word).
SDValue SubRegIdx = SDValue SubRegIdx =
CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
return SDValue(CurDAG->getMachineNode(PPC::EXTRACT_SUBREG, dl, MVT::i32, return SDValue(CurDAG->getMachineNode(PPC::EXTRACT_SUBREG, dl, MVT::i32,
NatWidthRes, SubRegIdx), 0); NatWidthRes, SubRegIdx), 0);
} }
// Produce a GPR sequence for compound comparisons (<=, >=) against zero.
// Handle both zero-extensions and sign-extensions.
SDValue PPCDAGToDAGISel::getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
nemanjaiAuthorUnsubmitted
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I realize that the three by-ref bool's makes this signature look kind of busy. Perhaps it would be better to just encode these as bits in a single char or something along those lines?

nemanjai: I realize that the three by-ref bool's makes this signature look kind of busy. Perhaps it would…
echristoUnsubmitted
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You don't appear to use the values anywhere after they're set or am I missing something?

echristo: You don't appear to use the values anywhere after they're set or am I missing something?
nemanjaiAuthorUnsubmitted
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The values are used after LLVM_FALLTHROUGH. For example line 2937, etc.

nemanjai: The values are used after `LLVM_FALLTHROUGH`. For example line 2937, etc.
ZeroCompare CmpTy) {
EVT InVT = LHS.getValueType();
bool Is32Bit = InVT == MVT::i32;
SDValue ToExtend;
// Produce the value that needs to be either zero or sign extended.
switch (CmpTy) {
default: llvm_unreachable("Unknown Zero-comparison type.");
case ZeroCompare::GEZExt:
case ZeroCompare::GESExt:
ToExtend = SDValue(CurDAG->getMachineNode(Is32Bit ? PPC::NOR : PPC::NOR8,
dl, InVT, LHS, LHS), 0);
case ZeroCompare::LEZExt:
case ZeroCompare::LESExt: {
if (Is32Bit) {
SDValue Neg =
SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
ToExtend =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
Neg, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
} else {
SDValue Addi =
SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
getI64Imm(~0ULL, dl)), 0);
ToExtend = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
Addi, LHS), 0);
}
}
}
// For 64-bit sequences, the extensions are the same for the GE/LE cases.
if (!Is32Bit && (CmpTy == ZeroCompare::GEZExt || ZeroCompare::LEZExt))
return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
ToExtend, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
if (!Is32Bit && (CmpTy == ZeroCompare::GESExt || ZeroCompare::LESExt))
return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, ToExtend,
getI64Imm(63, dl)), 0);
assert(Is32Bit && "Should have handled the 32-bit sequences above.");
// For 32-bit sequences, the extensions differ between GE/LE cases.
switch (CmpTy) {
default: llvm_unreachable("Unknown Zero-comparison type.");
case ZeroCompare::GEZExt: {
SDValue ShiftOps[] =
{ ToExtend, getI32Imm(1, dl), getI32Imm(31, dl), getI32Imm(31, dl) };
return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
ShiftOps), 0);
}
case ZeroCompare::GESExt:
return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, ToExtend,
nemanjaiAuthorUnsubmitted
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OK, I realize this shouldn't have been handled "above above". The commit will have just one "above". :)

nemanjai: OK, I realize this shouldn't have been handled "above above". The commit will have just one…
getI32Imm(31, dl)), 0);
case ZeroCompare::LEZExt:
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, ToExtend,
getI32Imm(1, dl)), 0);
case ZeroCompare::LESExt:
return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, ToExtend,
getI32Imm(-1, dl)), 0);
}
}
/// Produces a zero-extended result of comparing two 32-bit values according to /// Produces a zero-extended result of comparing two 32-bit values according to
/// the passed condition code. /// the passed condition code.
SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS, SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) { int64_t RHSValue, SDLoc dl) {
bool IsRHSZero = RHSValue == 0; bool IsRHSZero = RHSValue == 0;
bool IsRHSOne = RHSValue == 1;
bool IsRHSNegOne = RHSValue == -1LL;
nemanjaiAuthorUnsubmitted
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IsRHSOne/IsRHSNegOne are not currently used but will be used to produce the LHS <= 0 sequence for LHS < 1 and the LHS >= 0 sequence for LHS > -1 in a subsequent patch.

Rather than omitting them from this patch and the function that re-sets them, I left them in. This way if this isn't how we want to implement swapAndReset(), I can address it in this patch rather than having to re-work it in the next.

nemanjai: `IsRHSOne/IsRHSNegOne` are not currently used but will be used to produce the `LHS <= 0`…
echristoUnsubmitted
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I don't like committing dead code so let's try to avoid that.

The swapAndReset function is a little unusual. I'd probably just suggest grabbing the values you need as you need them rather than breaking it out into a function. Depending on how it looks I'd just comment the swap and fall through.

Thoughts?

echristo: I don't like committing dead code so let's try to avoid that. The swapAndReset function is a…
nemanjaiAuthorUnsubmitted
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Actually, I think that makes sense. At every place where we'd call that function, we just need to swap and set one of the three Boolean variables. I'll get rid of the function and put the code in the caller.

nemanjai: Actually, I think that makes sense. At every place where we'd call that function, we just need…
switch (CC) { switch (CC) {
default: return SDValue(); default: return SDValue();
case ISD::SETEQ: { case ISD::SETEQ: {
// (zext (setcc %a, %b, seteq)) -> (lshr (cntlzw (xor %a, %b)), 5) // (zext (setcc %a, %b, seteq)) -> (lshr (cntlzw (xor %a, %b)), 5)
// (zext (setcc %a, 0, seteq)) -> (lshr (cntlzw %a), 5) // (zext (setcc %a, 0, seteq)) -> (lshr (cntlzw %a), 5)
SDValue Xor = IsRHSZero ? LHS : SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0); SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
SDValue Clz = SDValue Clz =
Show All 12 Lines SDValue Clz =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0); SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl), SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl),
getI32Imm(31, dl) }; getI32Imm(31, dl) };
SDValue Shift = SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0); SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift, return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
getI32Imm(1, dl)), 0); getI32Imm(1, dl)), 0);
} }
case ISD::SETGE: {
// (zext (setcc %a, %b, setge)) -> (xor (lshr (sub %a, %b), 63), 1)
// (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 31)
if(IsRHSZero)
return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
std::swap(LHS, RHS);
echristoUnsubmitted
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Comment on these that we're going to swap and fallthrough?

echristo: Comment on these that we're going to swap and fallthrough?
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isNullValue();
LLVM_FALLTHROUGH;
}
case ISD::SETLE: {
// (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1)
// (zext (setcc %a, 0, setle)) -> (xor (lshr (- %a), 63), 1)
if(IsRHSZero)
return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
SDValue Sub =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Sub,
getI64Imm(1, dl), getI64Imm(63, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl,
MVT::i32, Shift, getI32Imm(1, dl)), 0);
}
} }
} }
/// Produces a sign-extended result of comparing two 32-bit values according to /// Produces a sign-extended result of comparing two 32-bit values according to
/// the passed condition code. /// the passed condition code.
SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS, SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) { int64_t RHSValue, SDLoc dl) {
bool IsRHSZero = RHSValue == 0; bool IsRHSZero = RHSValue == 0;
bool IsRHSOne = RHSValue == 1;
bool IsRHSNegOne = RHSValue == -1LL;
switch (CC) { switch (CC) {
default: return SDValue(); default: return SDValue();
case ISD::SETEQ: { case ISD::SETEQ: {
// (sext (setcc %a, %b, seteq)) -> // (sext (setcc %a, %b, seteq)) ->
// (ashr (shl (ctlz (xor %a, %b)), 58), 63) // (ashr (shl (ctlz (xor %a, %b)), 58), 63)
// (sext (setcc %a, 0, seteq)) -> // (sext (setcc %a, 0, seteq)) ->
// (ashr (shl (ctlz %a), 58), 63) // (ashr (shl (ctlz %a), 58), 63)
SDValue CountInput = IsRHSZero ? LHS : SDValue CountInput = IsRHSZero ? LHS :
Show All 22 Lines SDValue ShiftOps[] =
{ Clz, getI32Imm(27, dl), getI32Imm(5, dl), getI32Imm(31, dl) }; { Clz, getI32Imm(27, dl), getI32Imm(5, dl), getI32Imm(31, dl) };
SDValue Shift = SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0); SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
SDValue Xori = SDValue Xori =
SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift, SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
getI32Imm(1, dl)), 0); getI32Imm(1, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0); return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
} }
case ISD::SETGE: {
// (sext (setcc %a, %b, setge)) -> (add (lshr (sub %a, %b), 63), -1)
// (sext (setcc %a, 0, setge)) -> (ashr (~ %a), 31)
if (IsRHSZero)
return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
std::swap(LHS, RHS);
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isNullValue();
LLVM_FALLTHROUGH;
}
case ISD::SETLE: {
// (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1)
// (sext (setcc %a, 0, setle)) -> (add (lshr (- %a), 63), -1)
if (IsRHSZero)
return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
SDValue SUBFNode =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, MVT::Glue,
LHS, RHS), 0);
SDValue Srdi =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
SUBFNode, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Srdi,
getI32Imm(-1, dl)), 0);
}
} }
} }
/// Produces a zero-extended result of comparing two 64-bit values according to /// Produces a zero-extended result of comparing two 64-bit values according to
/// the passed condition code. /// the passed condition code.
SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS, SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) { int64_t RHSValue, SDLoc dl) {
▲ Show 20 Lines • Show All 2,274 Lines • Show Last 20 Lines

test/CodeGen/PowerPC/testComparesigesc.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_igesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesigesi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_igesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesigess.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_igess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesilesc.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesilesi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesiless.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_iless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesllgesc.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesllgesi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesllgess.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define i64 @test_llgess(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define void @test_llgess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testCompareslllesc.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define i64 @test_lllesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testCompareslllesi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define i64 @test_lllesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesllless.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define i64 @test_llless(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llless_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define void @test_llless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}