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[X86][SSE] Change BUILD_VECTOR interleaving ordering to improve coalescing/combine opportunities
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Authored by RKSimon on Jun 3 2017, 8:10 AM.

Details

Summary

We currently generate BUILD_VECTOR as a tree of UNPCKL shuffles of the same type:

e.g. for v4f32:

Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
      : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
Step 2: unpcklps X, Y ==>    <3, 2, 1, 0>

The issue is because we are not placing sequential vector elements together early enough, we fail to recognise many combinable patterns - consecutive scalar loads, extractions etc.

Instead, this patch unpacks progressively larger sequential vector elements together:

e.g. for v4f32:

Step 1: unpcklps 0, 2 ==> X: <?, ?, 1, 0>
      : unpcklps 1, 3 ==> Y: <?, ?, 3, 2>
Step 2: unpcklpd X, Y ==>    <3, 2, 1, 0>

This does mean that we are creating UNPCKL shuffle of different value types, but the relevant combines that benefit from this are quite capable of handling the additional BITCASTs that are now included in the shuffle tree.

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Repository
rL LLVM

Event Timeline

RKSimon created this revision.Jun 3 2017, 8:10 AM
zvi accepted this revision.Jun 4 2017, 11:57 AM

LGTM.

This revision is now accepted and ready to land.Jun 4 2017, 11:57 AM
This revision was automatically updated to reflect the committed changes.