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AMDGPU: Don't add same implicit use multiple times
ClosedPublic

Authored by arsenm on May 31 2017, 7:57 PM.

Reviewers

tstellar

Summary

For the last component, the same register use
was added as an implicit use and another implicit kill use.

ping

This revision is now accepted and ready to land.Jun 12 2017, 10:07 AM

r305205

Path

Size

lib/

Target/

AMDGPU/

6 lines

Show First 20 Lines • Show All 462 Lines • ▼ Show 20 Lines	for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
else		else
SubIdx = SubIndices[SubIndices.size() - Idx - 1];		SubIdx = SubIndices[SubIndices.size() - Idx - 1];

MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,		MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
get(Opcode), RI.getSubReg(DestReg, SubIdx));		get(Opcode), RI.getSubReg(DestReg, SubIdx));

Builder.addReg(RI.getSubReg(SrcReg, SubIdx));		Builder.addReg(RI.getSubReg(SrcReg, SubIdx));

if (Idx == SubIndices.size() - 1)
Builder.addReg(SrcReg, getKillRegState(KillSrc) \| RegState::Implicit);

if (Idx == 0)		if (Idx == 0)
Builder.addReg(DestReg, RegState::Define \| RegState::Implicit);		Builder.addReg(DestReg, RegState::Define \| RegState::Implicit);

Builder.addReg(SrcReg, RegState::Implicit);		bool UseKill = KillSrc && Idx == SubIndices.size() - 1;
		Builder.addReg(SrcReg, getKillRegState(UseKill) \| RegState::Implicit);
}		}
}		}

int SIInstrInfo::commuteOpcode(unsigned Opcode) const {		int SIInstrInfo::commuteOpcode(unsigned Opcode) const {
int NewOpc;		int NewOpc;

// Try to map original to commuted opcode		// Try to map original to commuted opcode
NewOpc = AMDGPU::getCommuteRev(Opcode);		NewOpc = AMDGPU::getCommuteRev(Opcode);
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