[PowerPC] Eliminate compares - add i64 sext/zext handling for equality

[nemanjai]

Summary

This patch adds the SETEQ patterns for i64 values.

[inouehrs]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

2860

Do you mean CA bit by addc.1?
IMO, {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1) or similar is clearer.
Someone may misunderstand that we need to execute addcarry twice with the current pseudo-code.

[nemanjai]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

2860

The idea was to use similar notation to that of the SDAG (i.e. result 0, result 1). But I do like your notation better. I'll change it as you suggested.

[echristo]

A few cosmetic changes in addition to the notation change that was mentioned (I also like that).

Otherwise LGTM.

-eric

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

2833

Seems to be unused at the moment?

2855

Ditto.

2928

Can you move this down to just before the first use?

[nemanjai]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

2833

It's actually used in deciding whether we use the LHS or (xor LSH, RHS) as the operand to count leading zeros.

2855

Same as above, but as input to add-immediate-with-carry instead of count leading zeros.

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

private:
     SDValue getLogicOpInGPR(SDValue LogicOp, LogicalOpsInGPR InGPR);
     SDValue signExtendInputIfNeeded(SDValue Input);
     SDValue zeroExtendInputIfNeeded(SDValue Input);
     SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv);
     SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                                 int64_t RHSValue, SDLoc dl);
     SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                                 int64_t RHSValue, SDLoc dl);
+    SDValue get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
+                                int64_t RHSValue, SDLoc dl);
+    SDValue get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
+                                int64_t RHSValue, SDLoc dl);
     SDValue getSETCCInGPR(SDValue Compare, SetccInGPROpts ConvOpts);
 
     void PeepholePPC64();
     void PeepholePPC64ZExt();
     void PeepholeCROps();
 
     SDValue combineToCMPB(SDNode *N);
     void foldBoolExts(SDValue &Res, SDNode *&N);
case ISD::SETEQ: {
     SDValue Sldi =
       SDValue(CurDAG->getMachineNode(PPC::RLDICR_32, dl, MVT::i32, SHLOps), 0);
     return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Sldi,
                                           getI32Imm(63, dl)), 0);
   }
   }
 }
 
+/// Produces a zero-extended result of comparing two 64-bit values according to
+/// the passed condition code.
+SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
+                                             ISD::CondCode CC,
+                                             int64_t RHSValue, SDLoc dl) {
+  bool IsRHSZero = RHSValue == 0;
+  switch (CC) {
+  default: return SDValue();
+  case ISD::SETEQ: {
+    // (zext (setcc %a, %b, seteq)) -> (lshr (ctlz (xor %a, %b)), 6)
+    // (zext (setcc %a, 0, seteq)) ->  (lshr (ctlz %a), 6)
+    SDValue Xor = IsRHSZero ? LHS :
+      SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
+    SDValue Clz =
+      SDValue(CurDAG->getMachineNode(PPC::CNTLZD, dl, MVT::i64, Xor), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Clz,
+                                          getI64Imm(58, dl), getI64Imm(63, dl)),
+                   0);
+  }
+  }
+}
+
+/// Produces a sign-extended result of comparing two 64-bit values according to
+/// the passed condition code.
+SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS,
+                                             ISD::CondCode CC,
+                                             int64_t RHSValue, SDLoc dl) {
+  bool IsRHSZero = RHSValue == 0;
+  switch (CC) {
+  default: return SDValue();
+  case ISD::SETEQ: {
+    // addc.0 = (addcarry (xor %a, %b), -1)
+    // addc.1 = (addcarry (xor %a, %b), -1).1
+    // (sext (setcc %a, %b, seteq)) -> (sube addc.0, addc.0, addc.1)
+    // addcz.0 = (addcarry %a, -1)
+    // sddcz.1 = (addcarry %a, -1).1
+    // (sext (setcc %a, 0, seteq)) -> (sube addcz.0, addcz.0, addcz.1)
+    SDValue AddInput = IsRHSZero ? LHS :
+      SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
+    SDValue Addic =
+      SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
+                                     AddInput, getI32Imm(~0U, dl)), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, Addic,
+                                          Addic, Addic.getValue(1)), 0);
+  }
+  }
+}
+
 /// Does this SDValue have any uses for which keeping the value in a GPR is
 /// appropriate. This is meant to be used on values that have type i1 since
 /// it is somewhat meaningless to ask if values of other types can be kept in
 /// GPR's.
 static bool allUsesExtend(SDValue Compare, SelectionDAG *CurDAG) {
   assert(Compare.getOpcode() == ISD::SETCC &&
          "An ISD::SETCC node required here.");
 
SDValue PPCDAGToDAGISel::getSETCCInGPR(SDValue Compare,
   SDValue LHS = Compare.getOperand(0);
   SDValue RHS = Compare.getOperand(1);
 
   // The condition code is operand 2 for SETCC and operand 4 for SELECT_CC.
   int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2;
   ISD::CondCode CC =
     cast<CondCodeSDNode>(Compare.getOperand(CCOpNum))->get();
   EVT InputVT = LHS.getValueType();
-  if (InputVT != MVT::i32)
+  if (InputVT != MVT::i32 && InputVT != MVT::i64)
     return SDValue();
 
   SDLoc dl(Compare);
   ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
+  bool Inputs32Bit = InputVT == MVT::i32;
   int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX;
 
   if (ConvOpts == SetccInGPROpts::ZExtInvert ||
       ConvOpts == SetccInGPROpts::SExtInvert)
     CC = ISD::getSetCCInverse(CC, true);
 
-  if (ISD::isSignedIntSetCC(CC)) {
+  if (ISD::isSignedIntSetCC(CC) && Inputs32Bit) {
     LHS = signExtendInputIfNeeded(LHS);
     RHS = signExtendInputIfNeeded(RHS);
-  } else if (ISD::isUnsignedIntSetCC(CC)) {
+  } else if (ISD::isUnsignedIntSetCC(CC) && Inputs32Bit) {
     LHS = zeroExtendInputIfNeeded(LHS);
     RHS = zeroExtendInputIfNeeded(RHS);
   }
 
   bool IsSext = ConvOpts == SetccInGPROpts::SExtOrig ||
     ConvOpts == SetccInGPROpts::SExtInvert;
-  if (IsSext)
+  if (IsSext && Inputs32Bit)
     return get32BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
+  else if (Inputs32Bit)
     return get32BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
+  else if (IsSext)
+    return get64BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
+  return get64BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
 }
 
 void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
   // Transfer memoperands.
   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
   MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
   cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
 }

test/CodeGen/PowerPC/expand-isel.ll

if.end:
   %conv3 = zext i1 %cmp to i32
   br label %cleanup
 
 cleanup:
   %retval.0 = phi i32 [ %conv3, %if.end ], [ 1, %entry ]
   ret i32 %retval.0
 
 ; CHECK-LABEL: @testComplexISEL
-; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
-; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
-; CHECK-NEXT:  [[TRUE]]
-; CHECK-NEXT: addi r3, r12, 0
-; CHECK-NEXT: [[SUCCESSOR]]
-; CHECK-NEXT: clrldi r3, r3, 32
-; CHECK-NEXT: blr
+; CHECK-DAG: [[LI:r[0-9]+]], 1
+; CHECK-DAG: cmplwi [[LD:r[0-9]+]], 0
+; CHECK: beq cr0, [[EQ:.LBB[0-9_]+]]
+; CHECK: blr
+; CHECK: [[EQ]]
+; CHECK: xor [[XOR:r[0-9]+]]
+; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
+; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63
 }
 
 !1 = !{!2, !2, i64 0}
 !2 = !{!"int", !3, i64 0}
 !3 = !{!"omnipotent char", !4, i64 0}
 !4 = !{!"Simple C/C++ TBAA"}

test/CodeGen/PowerPC/testComparesieqsll.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesieqsll.c'
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ieqsll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ieqsll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsll_z(i64 %a) {
+; CHECK-LABEL: test_ieqsll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsll_sext_z(i64 %a) {
+; CHECK-LABEL: test_ieqsll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ieqsll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ieqsll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsll_z_store(i64 %a) {
+; CHECK-LABEL: test_ieqsll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_ieqsll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}

test/CodeGen/PowerPC/testComparesiequll.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesiequll.c'
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iequll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iequll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequll_z(i64 %a) {
+; CHECK-LABEL: test_iequll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequll_sext_z(i64 %a) {
+; CHECK-LABEL: test_iequll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iequll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iequll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequll_z_store(i64 %a) {
+; CHECK-LABEL: test_iequll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_iequll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}

test/CodeGen/PowerPC/testCompareslleqsll.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lleqsll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lleqsll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsll_z(i64 %a) {
+; CHECK-LABEL: test_lleqsll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsll_sext_z(i64 %a) {
+; CHECK-LABEL: test_lleqsll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lleqsll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lleqsll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsll_z_store(i64 %a) {
+; CHECK-LABEL: test_lleqsll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_lleqsll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}

test/CodeGen/PowerPC/testComparesllequll.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llequll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llequll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequll_z(i64 %a) {
+; CHECK-LABEL: test_llequll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequll_sext_z(i64 %a) {
+; CHECK-LABEL: test_llequll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llequll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llequll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequll_z_store(i64 %a) {
+; CHECK-LABEL: test_llequll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llequll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}