Only enable LiveRangeShrink for x86.

[danielcdh]

Summary

Moving LiveRangeShrink to x86 as this pass is mostly useful for archtectures with great register pressure.

[qcolombet]

Thanks Dehao.
LGTM.

lib/CodeGen/TargetPassConfig.cpp

void TargetPassConfig::addMachinePasses() {
   if (getOptLevel() != CodeGenOpt::None) {
     addMachineSSAOptimization();
   } else {
     // If the target requests it, assign local variables to stack slots relative
     // to one another and simplify frame index references where possible.
     addPass(&LocalStackSlotAllocationID, false);
   }
 
-  if (getOptLevel() != CodeGenOpt::None)
-    addPass(&LiveRangeShrinkID);
-
   // Run pre-ra passes.
   addPreRegAlloc();
 
   // Run register allocation and passes that are tightly coupled with it,
   // including phi elimination and scheduling.
   if (getOptimizeRegAlloc())
     addOptimizedRegAlloc(createRegAllocPass(true));
   else

lib/Target/X86/X86TargetMachine.cpp

bool X86PassConfig::addPreISel() {
   const Triple &TT = TM->getTargetTriple();
   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
     addPass(createX86WinEHStatePass());
   return true;
 }
 
 void X86PassConfig::addPreRegAlloc() {
   if (getOptLevel() != CodeGenOpt::None) {
+    addPass(&LiveRangeShrinkID);
     addPass(createX86FixupSetCC());
     addPass(createX86OptimizeLEAs());
     addPass(createX86CallFrameOptimization());
   }
 
   addPass(createX86WinAllocaExpander());
 }
 

test/CodeGen/AArch64/arm64-ccmp.ll

 
 ; CHECK-LABEL: select_noccmp1
 define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
 ; CHECK: cmp x0, #0
 ; CHECK-NEXT: cset [[REG0:w[0-9]+]], lt
 ; CHECK-NEXT: cmp x0, #13
 ; CHECK-NOT: ccmp
 ; CHECK-NEXT: cset [[REG1:w[0-9]+]], gt
-; CHECK-NEXT: and [[REG4:w[0-9]+]], [[REG0]], [[REG1]]
 ; CHECK-NEXT: cmp x2, #2
 ; CHECK-NEXT: cset [[REG2:w[0-9]+]], lt
 ; CHECK-NEXT: cmp x2, #4
 ; CHECK-NEXT: cset [[REG3:w[0-9]+]], gt
+; CHECK-NEXT: and [[REG4:w[0-9]+]], [[REG0]], [[REG1]]
 ; CHECK-NEXT: and [[REG5:w[0-9]+]], [[REG2]], [[REG3]]
 ; CHECK-NEXT: orr [[REG6:w[0-9]+]], [[REG4]], [[REG5]]
 ; CHECK-NEXT: cmp [[REG6]], #0
 ; CHECK-NEXT: csel x0, xzr, x3, ne
 ; CHECK-NEXT: ret
   %c0 = icmp slt i64 %v1, 0
   %c1 = icmp sgt i64 %v1, 13
   %c2 = icmp slt i64 %v3, 2

test/CodeGen/NVPTX/sched1.ll

 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
 
 ; Ensure source scheduling is working
 
 define void @foo(i32* %a) {
 ; CHECK: .func foo
 ; CHECK: ld.u32
 ; CHECK-NEXT: ld.u32
-; CHECK-NEXT: add.s32
 ; CHECK-NEXT: ld.u32
-; CHECK-NEXT: add.s32
 ; CHECK-NEXT: ld.u32
 ; CHECK-NEXT: add.s32
+; CHECK-NEXT: add.s32
+; CHECK-NEXT: add.s32
   %ptr0 = getelementptr i32, i32* %a, i32 0
   %val0 = load i32, i32* %ptr0
   %ptr1 = getelementptr i32, i32* %a, i32 1
   %val1 = load i32, i32* %ptr1
   %ptr2 = getelementptr i32, i32* %a, i32 2
   %val2 = load i32, i32* %ptr2
   %ptr3 = getelementptr i32, i32* %a, i32 3
   %val3 = load i32, i32* %ptr3

test/CodeGen/NVPTX/sched2.ll

 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
 
 define void @foo(<2 x i32>* %a) {
 ; CHECK: .func foo
 ; CHECK: ld.v2.u32
 ; CHECK-NEXT: ld.v2.u32
+; CHECK-NEXT: ld.v2.u32
+; CHECK-NEXT: ld.v2.u32
 ; CHECK-NEXT: add.s32
 ; CHECK-NEXT: add.s32
-; CHECK-NEXT: ld.v2.u32
 ; CHECK-NEXT: add.s32
 ; CHECK-NEXT: add.s32
-; CHECK-NEXT: ld.v2.u32
 ; CHECK-NEXT: add.s32
 ; CHECK-NEXT: add.s32
   %ptr0 = getelementptr <2 x i32>, <2 x i32>* %a, i32 0
   %val0 = load <2 x i32>, <2 x i32>* %ptr0
   %ptr1 = getelementptr <2 x i32>, <2 x i32>* %a, i32 1
   %val1 = load <2 x i32>, <2 x i32>* %ptr1
   %ptr2 = getelementptr <2 x i32>, <2 x i32>* %a, i32 2
   %val2 = load <2 x i32>, <2 x i32>* %ptr2

test/CodeGen/SPARC/LeonItinerariesUT.ll

 ; LEON2_ITIN-NEXT:  ld 
 ; LEON2_ITIN-NEXT:  fmuls 
 ; LEON2_ITIN-NEXT:  retl 
 ; LEON2_ITIN-NEXT:  fdivs 
 
 ; LEON3_4_ITIN-LABEL: f32_ops:
 ; LEON3_4_ITIN:       ld 
 ; LEON3_4_ITIN-NEXT:  ld 
-; LEON3_4_ITIN-NEXT:  fadds 
 ; LEON3_4_ITIN-NEXT:  ld 
+; LEON3_4_ITIN-NEXT:  fadds 
 ; LEON3_4_ITIN-NEXT:  ld 
 ; LEON3_4_ITIN-NEXT:  fsubs 
 ; LEON3_4_ITIN-NEXT:  fmuls 
 ; LEON3_4_ITIN-NEXT:  retl 
 ; LEON3_4_ITIN-NEXT:  fdivs 
 
 define float @f32_ops(float* byval %a, float* byval %b, float* byval %c, float* byval %d) {
 entry: