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Differential D33147

[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
ClosedPublic

Authored by RKSimon on May 12 2017, 12:25 PM.

Details

Reviewers
jlebar
tra
qcolombet
sepavloff
Commits
rGa1978aaefd3a: [NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
rL302942: [NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
Summary

NVPTXTargetLowering::LowerReturn was trusting the default argument values.

This fixes 47 of the 75 NVPTX '-verify-machineinstrs with EXPENSIVE_CHECKS' errors in PR32146.

I've added -verify-machineinstrs to a few of the test files, I can be more thorough if you think it useful.

Diff Detail

Repository
rL LLVM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
NVPTX/
4 lines
test/
CodeGen/
NVPTX/
2 lines
2 lines
3 lines

Diff 98825

llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp

Show First 20 Lines • Show All 2,572 Lines • ▼ Show 20 Lines if (VectorInfo[i] & PVF_LAST) {
llvm_unreachable("Invalid vector info."); llvm_unreachable("Invalid vector info.");
} }
// Adjust type of load/store op if we've extended the scalar // Adjust type of load/store op if we've extended the scalar
// return value. // return value.
EVT TheStoreType = ExtendIntegerRetVal ? MVT::i32 : VTs[i]; EVT TheStoreType = ExtendIntegerRetVal ? MVT::i32 : VTs[i];
Chain = DAG.getMemIntrinsicNode(Op, dl, DAG.getVTList(MVT::Other), Chain = DAG.getMemIntrinsicNode(Op, dl, DAG.getVTList(MVT::Other),
StoreOperands, TheStoreType, StoreOperands, TheStoreType,
MachinePointerInfo(), 1); MachinePointerInfo(), /* Align */ 1,
/* Volatile */ false, /* ReadMem */ false,
/* WriteMem */ true, /* Size */ 0);
// Cleanup vector state. // Cleanup vector state.
StoreOperands.clear(); StoreOperands.clear();
} }
} }
return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain); return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
} }
▲ Show 20 Lines • Show All 2,072 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/NVPTX/ctlz.ll

; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
declare i16 @llvm.ctlz.i16(i16, i1) readnone declare i16 @llvm.ctlz.i16(i16, i1) readnone
declare i32 @llvm.ctlz.i32(i32, i1) readnone declare i32 @llvm.ctlz.i32(i32, i1) readnone
declare i64 @llvm.ctlz.i64(i64, i1) readnone declare i64 @llvm.ctlz.i64(i64, i1) readnone
; There should be no difference between llvm.ctlz.i32(%a, true) and ; There should be no difference between llvm.ctlz.i32(%a, true) and
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/NVPTX/ctpop.ll

; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
define i32 @myctpop(i32 %a) { define i32 @myctpop(i32 %a) {
; CHECK: popc.b32 ; CHECK: popc.b32
%val = tail call i32 @llvm.ctpop.i32(i32 %a) %val = tail call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %val ret i32 %val
} }
Show All 16 Lines

llvm/trunk/test/CodeGen/NVPTX/cttz.ll

; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
declare i16 @llvm.cttz.i16(i16, i1) readnone declare i16 @llvm.cttz.i16(i16, i1) readnone
declare i32 @llvm.cttz.i32(i32, i1) readnone declare i32 @llvm.cttz.i32(i32, i1) readnone
declare i64 @llvm.cttz.i64(i64, i1) readnone declare i64 @llvm.cttz.i64(i64, i1) readnone
define i32 @myctpop(i32 %a) { define i32 @myctpop(i32 %a) {
Show All 35 Lines