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[GISel]: Add support to translate ConstantVectors
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Authored by aditya_nandakumar on May 3 2017, 10:22 AM.

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qcolombet
ab
dsanders
volkan
javed.absar

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Repository: rL LLVM

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aditya_nandakumar created this revision.May 3 2017, 10:22 AM

Herald added a reviewer: javed.absar. · View Herald TranscriptMay 3 2017, 10:22 AM

Add missing tests.

Original diff was missing CHECK lines

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LGTM

This revision is now accepted and ready to land.May 4 2017, 1:57 PM

Committed in rL302196

Revision Contents

Path

Size

lib/

CodeGen/

GlobalISel/

IRTranslator.cpp

8 lines

test/

CodeGen/

AArch64/

GlobalISel/

arm64-irtranslator.ll

9 lines

Diff 97682

lib/CodeGen/GlobalISel/IRTranslator.cpp

Show First 20 Lines • Show All 1,102 Lines • ▼ Show 20 Lines	bool IRTranslator::translate(const Constant &C, unsigned Reg) {
} else if (auto CE = dyn_cast<ConstantExpr>(&C)) {		} else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
switch(CE->getOpcode()) {		switch(CE->getOpcode()) {
#define HANDLE_INST(NUM, OPCODE, CLASS) \		#define HANDLE_INST(NUM, OPCODE, CLASS) \
case Instruction::OPCODE: return translate##OPCODE(*CE, EntryBuilder);		case Instruction::OPCODE: return translate##OPCODE(*CE, EntryBuilder);
#include "llvm/IR/Instruction.def"		#include "llvm/IR/Instruction.def"
default:		default:
return false;		return false;
}		}
		} else if (auto CV = dyn_cast<ConstantVector>(&C)) {
		if (CV->getNumOperands() == 1)
		return translate(*CV->getOperand(0), Reg);
		SmallVector<unsigned, 4> Ops;
		for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
		Ops.push_back(getOrCreateVReg(*CV->getOperand(i)));
		}
		EntryBuilder.buildMerge(Reg, Ops);
} else		} else
return false;		return false;

return true;		return true;
}		}

void IRTranslator::finalizeFunction() {		void IRTranslator::finalizeFunction() {
// Release the memory used by the different maps we		// Release the memory used by the different maps we
▲ Show 20 Lines • Show All 115 Lines • Show Last 20 Lines

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

	Show First 20 Lines • Show All 1,535 Lines • ▼ Show 20 Lines
	; CHECK: [[C7:%[0-9]+]](s32) = G_CONSTANT i32 7			; CHECK: [[C7:%[0-9]+]](s32) = G_CONSTANT i32 7
	; CHECK: [[C15:%[0-9]+]](s32) = G_CONSTANT i32 15			; CHECK: [[C15:%[0-9]+]](s32) = G_CONSTANT i32 15
	; CHECK: [[MASK:%[0-9]+]](<16 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32)			; CHECK: [[MASK:%[0-9]+]](<16 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32)
	; CHECK: [[VEC:%[0-9]+]](<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>)			; CHECK: [[VEC:%[0-9]+]](<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>)
	; CHECK: %q0 = COPY [[VEC]](<16 x s8>)			; CHECK: %q0 = COPY [[VEC]](<16 x s8>)
	%res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>			%res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
	ret <16 x i8> %res			ret <16 x i8> %res
	}			}

				; CHECK-LABEL: test_constant_vector
				; CHECK: [[UNDEF:%[0-9]+]](s16) = IMPLICIT_DEF
				; CHECK: [[F:%[0-9]+]](s16) = G_FCONSTANT half 0xH3C00
				; CHECK: [[M:%[0-9]+]](<4 x s16>) = G_MERGE_VALUES [[UNDEF]](s16), [[UNDEF]](s16), [[UNDEF]](s16), [[F]](s16)
				; CHECK: %d0 = COPY [[M]](<4 x s16>)
				define <4 x half> @test_constant_vector() {
				ret <4 x half> <half undef, half undef, half undef, half 0xH3C00>
				}