[StackMaps] Increase the size of the "location size" field

[sanjoy]

Summary

In some cases LLVM (especially the SLP vectorizer) will create vectors
that are 256 bytes (or larger). Given that this is intentional[0] is
likely to get more common, this patch updates the StackMap binary
format to deal with the spill locations for said vectors.

This change also bumps the stack map version from 2 to 3.

[0]: https://reviews.llvm.org/D32533#738350

[reames]

LGTM

docs/StackMaps.rst

342 ↗

(On Diff #97031)

It's really unfortunate that we had to grow the size so much here, but given this is intended to be immediately parsed and thrown away, I guess it's not too much of a problem.

llvm/trunk/docs/StackMaps.rst

 
 The existence of a stack map or patch point intrinsic within an LLVM
 Module forces code emission to create a :ref:`stackmap-section`. The
 format of this section follows:
 
 .. code-block:: none
 
   Header {
-    uint8  : Stack Map Version (current version is 2)
+    uint8  : Stack Map Version (current version is 3)
     uint8  : Reserved (expected to be 0)
     uint16 : Reserved (expected to be 0)
   }
   uint32 : NumFunctions
   uint32 : NumConstants
   uint32 : NumRecords
   StkSizeRecord[NumFunctions] {
     uint64 : Function Address
     uint64 : Stack Size
     uint64 : Record Count
   }
   Constants[NumConstants] {
     uint64 : LargeConstant
   }
   StkMapRecord[NumRecords] {
     uint64 : PatchPoint ID
     uint32 : Instruction Offset
     uint16 : Reserved (record flags)
     uint16 : NumLocations
     Location[NumLocations] {
       uint8  : Register | Direct | Indirect | Constant | ConstantIndex
-      uint8  : Location Size
+      uint8  : Reserved (expected to be 0)
+      uint16 : Location Size
       uint16 : Dwarf RegNum
+      uint16 : Reserved (expected to be 0)
       int32  : Offset or SmallConstant
     }
+    uint32 : Padding (only if required to align to 8 byte)
     uint16 : Padding
     uint16 : NumLiveOuts
     LiveOuts[NumLiveOuts]
       uint16 : Dwarf RegNum
       uint8  : Reserved
       uint8  : Size in Bytes
     }
     uint32 : Padding (only if required to align to 8 byte)

llvm/trunk/lib/CodeGen/StackMaps.cpp

 #include <iterator>
 #include <utility>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "stackmaps"
 
 static cl::opt<int> StackMapVersion(
-    "stackmap-version", cl::init(2),
-    cl::desc("Specify the stackmap encoding version (default = 2)"));
+    "stackmap-version", cl::init(3),
+    cl::desc("Specify the stackmap encoding version (default = 3)"));
 
 const char *StackMaps::WSMP = "Stack Maps: ";
 
 StackMapOpers::StackMapOpers(const MachineInstr *MI)
   : MI(MI) {
   assert(getVarIdx() <= MI->getNumOperands() &&
          "invalid stackmap definition");
 }
while (ScratchIdx < e &&
            MI->getOperand(ScratchIdx).isEarlyClobber()))
     ++ScratchIdx;
 
   assert(ScratchIdx != e && "No scratch register available");
   return ScratchIdx;
 }
 
 StackMaps::StackMaps(AsmPrinter &AP) : AP(AP) {
-  if (StackMapVersion != 2)
+  if (StackMapVersion != 3)
     llvm_unreachable("Unsupported stackmap version!");
 }
 
 /// Go up the super-register chain until we hit a valid dwarf register number.
 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
   int RegNum = TRI->getDwarfRegNum(Reg, false);
   for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR)
     RegNum = TRI->getDwarfRegNum(*SR, false);
for (const auto &Loc : CSLocs) {
         break;
       case Location::Constant:
         OS << "Constant " << Loc.Offset;
         break;
       case Location::ConstantIndex:
         OS << "Constant Index " << Loc.Offset;
         break;
       }
-      OS << "\t[encoding: .byte " << Loc.Type << ", .byte " << Loc.Size
-         << ", .short " << Loc.Reg << ", .int " << Loc.Offset << "]\n";
+      OS << "\t[encoding: .byte " << Loc.Type << ", .byte 0"
+         << ", .short " << Loc.Size << ", .short " << Loc.Reg << ", .short 0"
+         << ", .int " << Loc.Offset << "]\n";
       Idx++;
     }
 
     OS << WSMP << "\thas " << LiveOuts.size() << " live-out registers\n";
 
     Idx = 0;
     for (const auto &LO : LiveOuts) {
       OS << WSMP << "\t\tLO " << Idx << ": ";
for (const auto &CSI : CSInfos) {
     OS.EmitValue(CSI.CSOffsetExpr, 4);
 
     // Reserved for flags.
     OS.EmitIntValue(0, 2);
     OS.EmitIntValue(CSLocs.size(), 2);
 
     for (const auto &Loc : CSLocs) {
       OS.EmitIntValue(Loc.Type, 1);
-      OS.EmitIntValue(Loc.Size, 1);
+      OS.EmitIntValue(0, 1);  // Reserved
+      OS.EmitIntValue(Loc.Size, 2);
       OS.EmitIntValue(Loc.Reg, 2);
+      OS.EmitIntValue(0, 2);  // Reserved
       OS.EmitIntValue(Loc.Offset, 4);
     }
 
+    // Emit alignment to 8 byte.
+    OS.EmitValueToAlignment(8);
+
     // Num live-out registers and padding to align to 4 byte.
     OS.EmitIntValue(0, 2);
     OS.EmitIntValue(LiveOuts.size(), 2);
 
     for (const auto &LO : LiveOuts) {
       OS.EmitIntValue(LO.DwarfRegNum, 2);
       OS.EmitIntValue(0, 1);
       OS.EmitIntValue(LO.Size, 1);

llvm/trunk/test/CodeGen/AArch64/arm64-anyregcc.ll

 ; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
 
 ; Stackmap Header: no constants - 6 callsites
 ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
 ; Header
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
 ; CHECK-NEXT:   .long 8
 ; Num LargeConstants
 ; CHECK-NEXT:   .long 0
 ; Num Callsites
 ; CHECK-NEXT:   .long 8

 
 ; test
 ; CHECK-LABEL:  .long   L{{.*}}-_test
 ; CHECK-NEXT:   .short  0
 ; 3 locations
 ; CHECK-NEXT:   .short  3
 ; Loc 0: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 4
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 4
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 4
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 4
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 2: Constant 3
 ; CHECK-NEXT:   .byte 4
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
+; CHECK-NEXT:   .short 0
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 3
 define i64 @test() nounwind ssp uwtable {
 entry:
   call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3)
   ret i64 0
 }
 
 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
 ; CHECK-LABEL:  .long   L{{.*}}-_property_access1
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 281474417671919 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj)
   ret i64 %ret
 }
 
 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
 ; CHECK-LABEL:  .long   L{{.*}}-_property_access2
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @property_access2() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 281474417671919 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj)
   ret i64 %ret
 }
 
 ; property access 3 - %obj is a frame index
 ; CHECK-LABEL:  .long   L{{.*}}-_property_access3
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Direct FP - 8
 ; CHECK-NEXT:   .byte 2
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short 29
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long -8
 define i64 @property_access3() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 281474417671919 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj)
   ret i64 %ret
 }
 
 ; anyreg_test1
 ; CHECK-LABEL:  .long   L{{.*}}-_anyreg_test1
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short 0
 ; 14 locations
 ; CHECK-NEXT:   .short  14
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 2: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 3: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 4: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 5: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 6: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 7: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 8: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 9: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 10: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 11: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 12: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 13: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 281474417671919 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
   ret i64 %ret
 }
 
 ; anyreg_test2
 ; CHECK-LABEL:  .long   L{{.*}}-_anyreg_test2
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short 0
 ; 14 locations
 ; CHECK-NEXT:   .short  14
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 2: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 3: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 4: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 5: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 6: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 7: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 8: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 9: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 10: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 11: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 12: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 13: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 281474417671919 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
   ret i64 %ret
 }
 
 ; Test spilling the return value of an anyregcc call.
 ;
 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
 ;
 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .short 3
 ; Loc 0: Register (some register that will be spilled to the stack)
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 1: Register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 1: Register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
   tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
   ret i64 %result
 }
 
 ; Test spilling the arguments of an anyregcc call.
 ;
 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
 ;
 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .short 5
 ; Loc 0: Return a register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 1: Arg0 in a Register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 2: Arg1 in a Register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 3: Arg2 spilled to FP -96
 ; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short 29
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long -96
 ; Loc 4: Arg3 spilled to FP - 88
 ; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short 29
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long -88
 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
   %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   ret i64 %result
 }
 
 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)

llvm/trunk/test/CodeGen/AArch64/arm64-stackmap.ll

 ; RUN: llc -mtriple=arm64-apple-darwin -mattr=+reserve-x18                             < %s | FileCheck %s
 ; RUN: llc -mtriple=arm64-apple-darwin -mattr=+reserve-x18 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
 ;
 ; Note: Print verbose stackmaps using -debug-only=stackmaps.
 
 ; We are not getting the correct stack alignment when cross compiling for arm64.
 ; So specify a datalayout here.
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 
 ; CHECK-LABEL:  .section  __LLVM_STACKMAPS,__llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
 ; Header
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
 ; CHECK-NEXT:   .long 11
 ; Num LargeConstants
 ; CHECK-NEXT:   .long 2
 ; Num Callsites
 ; CHECK-NEXT:   .long 11

 ; Constant arguments
 ;
 ; CHECK-NEXT:   .quad   1
 ; CHECK-NEXT:   .long   L{{.*}}-_constantargs
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  4
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   65535
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   65536
 ; SmallConstant
 ; CHECK-NEXT:   .byte   5
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; LargeConstant at index 0
 ; CHECK-NEXT:   .byte   5
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   1
 
 define void @constantargs() {
 entry:
   %0 = inttoptr i64 244837814094590 to i8*
   tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 20, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296)
   ret void
 }
 
 ; Inline OSR Exit
 ;
 ; CHECK-LABEL:  .long   L{{.*}}-_osrinline
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long  0
 define void @osrinline(i64 %a, i64 %b) {
 entry:
   ; Runtime void->void call.
   call void inttoptr (i64 244837814094590 to void ()*)()
   ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
   ret void
 }
 
 ; Cold OSR Exit
 ;
 ; 2 live variables in register.
 ;
 ; CHECK-LABEL:  .long   L{{.*}}-_osrcold
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long  0
 define void @osrcold(i64 %a, i64 %b) {
 entry:
   %test = icmp slt i64 %a, %b
   br i1 %test, label %ret, label %cold
 cold:
   ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
   %thunk = inttoptr i64 244837814094590 to i8*
entry:
   ret i64 %add
 }
 
 ; Property Write
 ; CHECK-LABEL:  .long   L{{.*}}-_propertyWrite
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
 entry:
   %resolveWrite = inttoptr i64 244837814094590 to i8*
   call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
   ret void
 }
 
 ; Void JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK-LABEL:  .long   L{{.*}}-_jsVoidCall
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
   %resolveCall = inttoptr i64 244837814094590 to i8*
   call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
   ret void
 }
 
 ; i64 JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK-LABEL:  .long   L{{.*}}-_jsIntCall
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
   %resolveCall = inttoptr i64 244837814094590 to i8*
   %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 28 stack map entries.
 ;
 ; CHECK-LABEL:  .long L{{.*}}-_spilledValue
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 28
 ;
 ; Check that at least one is a spilled entry from RBP.
 ; Location: Indirect FP + ...
 ; CHECK:        .byte 3
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 
 ; CHECK-NEXT:   .short 29
+; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .long
 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) {
 entry:
   call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 20, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
   ret void
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 23 stack map entries.
 ;
 ; CHECK-LABEL:  .long L{{.*}}-_spilledStackMapValue
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 30
 ;
 ; Check that at least one is a spilled entry from RBP.
 ; Location: Indirect FP + ...
 ; CHECK:        .byte 3
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 
 ; CHECK-NEXT:   .short 29
+; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .long
 define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) {
 entry:
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29)
   ret void
 }
 
 
 ; Map a constant value.
 ;
 ; CHECK-LABEL:  .long L{{.*}}-_liveConstant
 ; CHECK-NEXT:   .short 0
 ; 1 location
 ; CHECK-NEXT:   .short 1
 ; Loc 0: SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   33
 
 define void @liveConstant() {
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 8, i32 33)
   ret void
 }
 
 ; Map a value when LR is the only free register.
 ;
 ; CHECK-LABEL:  .long L{{.*}}-_clobberLR
 ; CHECK-NEXT:   .short 0
 ; 1 location
 ; CHECK-NEXT:   .short 1
 ; Loc 0: Indirect FP (r29) - offset
 ; CHECK-NEXT:   .byte   3
-; CHECK-NEXT:   .byte   4
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  4
 ; CHECK-NEXT:   .short  29
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -{{[0-9]+}}
 define void @clobberLR(i32 %a) {
   tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x31}"() nounwind
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
   ret void
 }
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)

llvm/trunk/test/CodeGen/AArch64/stackmap-liveness.ll

 ; RUN: llc < %s -mtriple=aarch64-apple-darwin | FileCheck %s
 
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
 ; CHECK-LABEL:  .section  __LLVM_STACKMAPS,__llvm_stackmaps
 ; CHECK-NEXT:   __LLVM_StackMaps:
 ; Header
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
 ; CHECK-NEXT:   .long 1
 ; Num LargeConstants
 ; CHECK-NEXT:   .long   0
 ; Num Callsites
 ; CHECK-NEXT:   .long   1
 
 ; Functions and stack size
 ; CHECK-NEXT:   .quad _stackmap_liveness
 ; CHECK-NEXT:   .quad 16
 
 ; Test that the return register is recognized as an live-out.
 define i64 @stackmap_liveness(i1 %c) {
 ; CHECK-LABEL:  .long L{{.*}}-_stackmap_liveness
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; Padding
+; CHECK-NEXT:   .p2align  3
 ; CHECK-NEXT:   .short  0
 ; Num LiveOut Entries: 1
 ; CHECK-NEXT:   .short  2
 ; LiveOut Entry 0: X0
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .byte 8
 ; LiveOut Entry 1: SP

llvm/trunk/test/CodeGen/PowerPC/ppc64-anyregcc.ll

 ; CHECK-LABEL: patchpoint_spillargs:
 ; CHECK: {{^}}.L[[patchpoint_spillargs_BEGIN:.*]]:{{$}}
 
 
 ; Stackmap Header: no constants - 6 callsites
 ; CHECK-LABEL: .section .llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
 ; Header
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
 ; CHECK-NEXT:   .long 8
 ; Num LargeConstants
 ; CHECK-NEXT:   .long 0
 ; Num Callsites
 ; CHECK-NEXT:   .long 8

 
 ; test
 ; CHECK:  .long   .L{{.*}}-.L[[test_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; 3 locations
 ; CHECK-NEXT:   .short  3
 ; Loc 0: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 4
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 4
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 4
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 4
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 2: Constant 3
 ; CHECK-NEXT:   .byte 4
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
+; CHECK-NEXT:   .short 0
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 3
 define i64 @test() nounwind ssp uwtable {
 entry:
   call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 40, i8* null, i32 2, i32 1, i32 2, i64 3)
   ret i64 0
 }
 
 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
 ; CHECK:  .long   .L{{.*}}-.L[[property_access1_BEGIN]]
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 281474417671919 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 40, i8* %f, i32 1, i8* %obj)
   ret i64 %ret
 }
 
 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
 ; CHECK:  .long   .L{{.*}}-.L[[property_access2_BEGIN]]
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @property_access2() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 281474417671919 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 40, i8* %f, i32 1, i64* %obj)
   ret i64 %ret
 }
 
 ; property access 3 - %obj is a frame index
 ; CHECK:  .long   .L{{.*}}-.L[[property_access3_BEGIN]]
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Direct FP - 8
 ; CHECK-NEXT:   .byte 2
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short 31
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 112
 define i64 @property_access3() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 281474417671919 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 40, i8* %f, i32 0, i64* %obj)
   ret i64 %ret
 }
 
 ; anyreg_test1
 ; CHECK:  .long   .L{{.*}}-.L[[anyreg_test1_BEGIN]]
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short 0
 ; 14 locations
 ; CHECK-NEXT:   .short  14
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 2: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 3: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 4: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 5: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 6: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 7: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 8: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 9: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 10: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 11: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 12: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 13: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 281474417671919 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 40, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
   ret i64 %ret
 }
 
 ; anyreg_test2
 ; CHECK:  .long   .L{{.*}}-.L[[anyreg_test2_BEGIN]]
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short 0
 ; 14 locations
 ; CHECK-NEXT:   .short  14
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 2: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 3: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 4: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 5: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 6: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 7: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 8: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 9: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 10: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 11: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 12: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 13: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 281474417671919 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 40, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
   ret i64 %ret
 }
 
 ; Test spilling the return value of an anyregcc call.
 ;
 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
 ;
 ; CHECK: .long .L{{.*}}-.L[[patchpoint_spilldef_BEGIN]]
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .short 3
 ; Loc 0: Register (some register that will be spilled to the stack)
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 1: Register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 1: Register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 40, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
   tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
 },~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
   ret i64 %result
 }
 
 ; Test spilling the arguments of an anyregcc call.
 ;
 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
 ;
 ; CHECK: .long .L{{.*}}-.L[[patchpoint_spillargs_BEGIN]]
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .short 5
 ; Loc 0: Return a register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 1: Arg0 in a Register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 2: Arg1 in a Register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 3: Arg2 spilled to FP -96
 ; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short 31
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long 128
 ; Loc 4: Arg3 spilled to FP - 88
 ; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
 ; CHECK-NEXT: .short 31
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long 136
 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
 },~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
   %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 40, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   ret i64 %result
 }
 
 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)

llvm/trunk/test/CodeGen/PowerPC/ppc64-stackmap.ll

 
 ; CHECK-LABEL: clobberLR:
 ; CHECK: {{^}}.L[[clobberLR_BEGIN:.*]]:{{$}}
 
 
 ; CHECK-LABEL:  .section  .llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
 ; Header
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
 ; CHECK-NEXT:   .long 11
 ; Num LargeConstants
 ; CHECK-NEXT:   .long 2
 ; Num Callsites
 ; CHECK-NEXT:   .long 11

 ; Constant arguments
 ;
 ; CHECK-NEXT:   .quad   1
 ; CHECK-NEXT:   .long   .L{{.*}}-.L[[constantargs_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  4
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   65535
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   65536
 ; SmallConstant
 ; CHECK-NEXT:   .byte   5
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; LargeConstant at index 0
 ; CHECK-NEXT:   .byte   5
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   1
 
 define void @constantargs() {
 entry:
   %0 = inttoptr i64 244837814094590 to i8*
   tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 40, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296)
   ret void
 }
 
 ; Inline OSR Exit
 ;
 ; CHECK:  .long   .L{{.*}}-.L[[osrinline_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long  0
 define void @osrinline(i64 %a, i64 %b) {
 entry:
   ; Runtime void->void call.
   call void inttoptr (i64 244837814094590 to void ()*)()
   ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
   ret void
 }
 
 ; Cold OSR Exit
 ;
 ; 2 live variables in register.
 ;
 ; CHECK:  .long   .L{{.*}}-.L[[osrcold_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long  0
 define void @osrcold(i64 %a, i64 %b) {
 entry:
   %test = icmp slt i64 %a, %b
   br i1 %test, label %ret, label %cold
 cold:
   ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
   %thunk = inttoptr i64 244837814094590 to i8*
entry:
   ret i64 %add
 }
 
 ; Property Write
 ; CHECK:  .long   .L{{.*}}-.L[[propertyWrite_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
 entry:
   %resolveWrite = inttoptr i64 244837814094590 to i8*
   call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 40, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
   ret void
 }
 
 ; Void JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK:  .long   .L{{.*}}-.L[[jsVoidCall_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
   %resolveCall = inttoptr i64 244837814094590 to i8*
   call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 40, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
   ret void
 }
 
 ; i64 JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK:  .long   .L{{.*}}-.L[[jsIntCall_BEGIN]]
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
   %resolveCall = inttoptr i64 244837814094590 to i8*
   %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 40, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 28 stack map entries.
 ;
 ; CHECK:  .long .L{{.*}}-.L[[spilledValue_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 28
 ;
 ; Check that at least one is a spilled entry from r31.
 ; Location: Indirect FP + ...
 ; CHECK:        .byte 3
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 
 ; CHECK-NEXT:   .short 31
+; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .long
 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) {
 entry:
   call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 40, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
   ret void
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 30 stack map entries.
 ;
 ; CHECK:  .long .L{{.*}}-.L[[spilledStackMapValue_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 30
 ;
 ; Check that at least one is a spilled entry from r31.
 ; Location: Indirect FP + ...
 ; CHECK:        .byte 3
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short 
 ; CHECK-NEXT:   .short 31
+; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .long
 define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) {
 entry:
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29)
   ret void
 }
 
 
 ; Map a constant value.
 ;
 ; CHECK:  .long .L{{.*}}-.L[[liveConstant_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; 1 location
 ; CHECK-NEXT:   .short 1
 ; Loc 0: SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   33
 
 define void @liveConstant() {
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 8, i32 33)
   ret void
 }
 
 ; Map a value when LR is the only free register.
 ;
 ; CHECK:  .long .L{{.*}}-.L[[clobberLR_BEGIN]]
 ; CHECK-NEXT:   .short 0
 ; 1 location
 ; CHECK-NEXT:   .short 1
 ; Loc 0: Indirect FP (r31) - offset
 ; CHECK-NEXT:   .byte   3
-; CHECK-NEXT:   .byte   4
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  4
 ; CHECK-NEXT:   .short  31
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   {{[0-9]+}}
 define void @clobberLR(i32 %a) {
   tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
   ret void
 }
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)

llvm/trunk/test/CodeGen/X86/anyregcc.ll

 ; RUN: llc < %s -mtriple=x86_64-apple-darwin                  -disable-fp-elim | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7     -disable-fp-elim | FileCheck --check-prefix=SSE %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -disable-fp-elim | FileCheck --check-prefix=AVX %s
 
 
 ; Stackmap Header: no constants - 6 callsites
 ; CHECK-LABEL:  .section __LLVM_STACKMAPS,__llvm_stackmaps
 ; CHECK-NEXT:   __LLVM_StackMaps:
 ; Header
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
 ; CHECK-NEXT:   .long 8
 ; Num Constants
 ; CHECK-NEXT:   .long 0
 ; Num Callsites
 ; CHECK-NEXT:   .long 8

 ; Callsites
 ; test
 ; CHECK-LABEL:  .long   L{{.*}}-_test
 ; CHECK-NEXT:   .short  0
 ; 3 locations
 ; CHECK-NEXT:   .short  3
 ; Loc 0: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 4
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 4
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 4
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 4
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 2: Constant 3
 ; CHECK-NEXT:   .byte 4
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
+; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 3
 define i64 @test() nounwind ssp uwtable {
 entry:
   call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 15, i8* null, i32 2, i32 1, i32 2, i64 3)
   ret i64 0
 }
 
 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
 ; CHECK-LABEL:  .long   L{{.*}}-_property_access1
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 12297829382473034410 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 15, i8* %f, i32 1, i8* %obj)
   ret i64 %ret
 }
 
 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
 ; CHECK-LABEL:  .long   L{{.*}}-_property_access2
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @property_access2() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 12297829382473034410 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %f, i32 1, i64* %obj)
   ret i64 %ret
 }
 
 ; property access 3 - %obj is a frame index
 ; CHECK-LABEL:  .long   L{{.*}}-_property_access3
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Direct RBP - ofs
 ; CHECK-NEXT:   .byte 2
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short 6
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long
 define i64 @property_access3() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 12297829382473034410 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 15, i8* %f, i32 0, i64* %obj)
   ret i64 %ret
 }
 
 ; anyreg_test1
 ; CHECK-LABEL:  .long   L{{.*}}-_anyreg_test1
 ; CHECK-NEXT:   .short  0
 ; 14 locations
 ; CHECK-NEXT:   .short  14
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 2: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 3: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 4: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 5: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 6: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 7: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 8: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 9: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 10: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 11: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 12: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 13: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 12297829382473034410 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 15, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
   ret i64 %ret
 }
 
 ; anyreg_test2
 ; CHECK-LABEL:  .long   L{{.*}}-_anyreg_test2
 ; CHECK-NEXT:   .short  0
 ; 14 locations
 ; CHECK-NEXT:   .short  14
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 1: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 2: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 3: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 4: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 5: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 6: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 7: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 8: Register
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 ; Loc 9: Argument, still on stack
 ; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long
 ; Loc 10: Argument, still on stack
 ; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long
 ; Loc 11: Argument, still on stack
 ; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long
 ; Loc 12: Argument, still on stack
 ; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long
 ; Loc 13: Argument, still on stack
 ; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long
 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
 entry:
   %f = inttoptr i64 12297829382473034410 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
   ret i64 %ret
 }
 
 ; Test spilling the return value of an anyregcc call.
 ;
 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
 ;
 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .short 3
 ; Loc 0: Register (some register that will be spilled to the stack)
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 1: Register RDI
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short 5
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 1: Register RSI
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short 4
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
   tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
   ret i64 %result
 }
 
 ; Test spilling the arguments of an anyregcc call.
 ;
 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
 ;
 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
 ; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .short 5
 ; Loc 0: Return a register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 1: Arg0 in a Register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 2: Arg1 in a Register
 ; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long  0
 ; Loc 3: Arg2 spilled to RBP +
 ; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long
 ; Loc 4: Arg3 spilled to RBP +
 ; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
+; CHECK-NEXT: .byte  0
+; CHECK-NEXT: .short  8
 ; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
 ; CHECK-NEXT: .long
 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
   %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   ret i64 %result
 }
 

llvm/trunk/test/CodeGen/X86/deopt-bundles.ll

 ; RUN: llc     < %s | FileCheck %s
 ; RUN: llc -O3 < %s | FileCheck %s
 ; RUN: llc -O3 -debug-only=stackmaps < %s 2>&1 | FileCheck -check-prefix=STACKMAPS %s
 ; REQUIRES: asserts
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.11.0"
 
 
 ; STACKMAPS: Stack Maps: callsite 2882400015
 ; STACKMAPS-NEXT: Stack Maps:   has 4 locations
-; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1]
-; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1]
+; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
 ; STACKMAPS-NEXT: Stack Maps:   has 0 live-out registers
 ; STACKMAPS-NEXT: Stack Maps: callsite 4242
 ; STACKMAPS-NEXT: Stack Maps:   has 4 locations
-; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1]
-; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1]
+; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1]
+; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1]
 ; STACKMAPS-NEXT: Stack Maps:   has 0 live-out registers
 ; STACKMAPS-NEXT: Stack Maps: callsite 4243
 ; STACKMAPS-NEXT: Stack Maps:   has 4 locations
-; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1]
-; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 16  [encoding: .byte 4, .byte 8, .short 0, .int 16]
+; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1]
+; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 16  [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 16]
 ; STACKMAPS-NEXT: Stack Maps:   has 0 live-out registers
 ; STACKMAPS-NEXT: Stack Maps: callsite 2882400015
 ; STACKMAPS-NEXT: Stack Maps:   has 4 locations
-; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1]
-; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 2 [encoding: .byte 4, .byte 8, .short 0, .int 2]
+; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1]
+; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 2 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 2]
 ; STACKMAPS-NEXT: Stack Maps:   has 0 live-out registers
 ; STACKMAPS-NEXT: Stack Maps: callsite 2882400015
 ; STACKMAPS-NEXT: Stack Maps:   has 4 locations
-; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1]
-; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 3 [encoding: .byte 4, .byte 8, .short 0, .int 3]
+; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1]
+; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 3 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 3]
 ; STACKMAPS-NEXT: Stack Maps:   has 0 live-out registers
 ; STACKMAPS-NEXT: Stack Maps: callsite 4243
 ; STACKMAPS-NEXT: Stack Maps:   has 4 locations
-; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1]
-; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 55  [encoding: .byte 4, .byte 8, .short 0, .int 55]
+; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1]
+; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 55  [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 55]
 ; STACKMAPS-NEXT: Stack Maps:   has 0 live-out registers
 
 declare i32 @callee_0()
 declare i32 @callee_1(i32)
 declare i32 @callee_vararg(...)
 
 define i32 @caller_0() {
 ; CHECK-LABEL: _caller_0

 ; CHECK-NEXT: movaps  %xmm3, 48(%rsp)
 ; CHECK-NEXT: movaps  %xmm2, 32(%rsp)
 ; CHECK-NEXT: movaps  %xmm1, 16(%rsp)
 ; CHECK-NEXT: movaps  %xmm0, (%rsp)
   call void @unknown() [ "deopt"(<32 x i64 addrspace(1)*> %val) ]
   ret void
 ; STACKMAPS: Stack Maps: callsite 2882400015
 ; STACKMAPS-NEXT: Stack Maps:   has 4 locations
-; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1]
-; STACKMAPS-NEXT: Stack Maps:     Loc 3: Indirect 7+0 [encoding: .byte 3, .byte 256, .short 7, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1]
+; STACKMAPS-NEXT: Stack Maps:     Loc 3: Indirect 7+0 [encoding: .byte 3, .byte 0, .short 256, .short 7, .short 0, .int 0]
 ; STACKMAPS-NEXT: Stack Maps:   has 0 live-out registers
 }
 
 declare void @unknown()

llvm/trunk/test/CodeGen/X86/deopt-intrinsic-cconv.ll

 entry:
   %v = call webkit_jscc i64(...) @llvm.experimental.deoptimize.i64(i32 42, float 500.0) [ "deopt"(i32 3) ]
   ret i64 %v
 }
 
 ; STACKMAPS: Stack Maps: callsites:
 ; STACKMAPS-NEXT: Stack Maps: callsite 2882400015
 ; STACKMAPS-NEXT: Stack Maps:   has 4 locations
-; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 12  [encoding: .byte 4, .byte 8, .short 0, .int 12]
-; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1]
-; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 3 [encoding: .byte 4, .byte 8, .short 0, .int 3]
+; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 12  [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 12]
+; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1]
+; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 3 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 3]
 ; STACKMAPS-NEXT: Stack Maps:   has 0 live-out registers

llvm/trunk/test/CodeGen/X86/deopt-intrinsic.ll

 entry:
   %v = call i8(...) @llvm.experimental.deoptimize.i8(i32 42, float 500.0) [ "deopt"(i32 1) ]
   ret i8 %v
 }
 
 ; STACKMAPS: Stack Maps: callsites:
 ; STACKMAPS-NEXT: Stack Maps: callsite 2882400015
 ; STACKMAPS-NEXT: Stack Maps:   has 4 locations
-; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1]
-; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1]
+; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
 ; STACKMAPS-NEXT: Stack Maps:   has 0 live-out registers
 ; STACKMAPS-NEXT: Stack Maps: callsite 2882400015
 ; STACKMAPS-NEXT: Stack Maps:   has 4 locations
-; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0]
-; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1]
-; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1]
+; STACKMAPS-NEXT: Stack Maps:     Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0]
+; STACKMAPS-NEXT: Stack Maps:     Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1]
+; STACKMAPS-NEXT: Stack Maps:     Loc 3: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1]
 ; STACKMAPS-NEXT: Stack Maps:   has 0 live-out registers

llvm/trunk/test/CodeGen/X86/patchpoint-invoke.ll

 ; Verify that the unwind data covers the entire patchpoint region:
 ; CHECK-NEXT: .long .Ltmp0-[[FUNC_BEGIN]]
 ; CHECK-NEXT: .long [[PP_END]]-.Ltmp0
 
 
 ; Verify that the stackmap section got emitted:
 ; CHECK-LABEL: __LLVM_StackMaps:
 ; Header
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
 ; CHECK-NEXT:   .long 1
 ; Num LargeConstants
 ; CHECK-NEXT:   .long 0
 ; Num Callsites
 ; CHECK-NEXT:   .long 1
 ; CHECK-NEXT:   .quad patchpoint_invoke
 
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
 declare i32 @__gxx_personality_v0(...)

llvm/trunk/test/CodeGen/X86/stackmap-fast-isel.ll

 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7                             | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; CHECK-LABEL:  .section  __LLVM_STACKMAPS,__llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
 ; Header
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
 ; CHECK-NEXT:   .long 4
 ; Num LargeConstants
 ; CHECK-NEXT:   .long 3
 ; Num Callsites
 ; CHECK-NEXT:   .long 7

 ; Constant arguments
 ;
 ; CHECK-NEXT:   .quad   1
 ; CHECK-NEXT:   .long   L{{.*}}-_constantargs
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  12
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -1
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -1
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   65536
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   2000000000
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   2147483647
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -1
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -1
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; LargeConstant at index 0
 ; CHECK-NEXT:   .byte   5
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; LargeConstant at index 1
 ; CHECK-NEXT:   .byte   5
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   1
 ; LargeConstant at index 2
 ; CHECK-NEXT:   .byte   5
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   2
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -1
 
 define void @constantargs() {
 entry:
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 1, i32 15, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1)
   ret void
 }
 
 ; Map a constant value.
 ;
 ; CHECK-LABEL:  .long L{{.*}}-_liveConstant
 ; CHECK-NEXT:   .short 0
 ; 1 location
 ; CHECK-NEXT:   .short 1
 ; Loc 0: SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   33
 
 define void @liveConstant() {
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 5, i32 33)
   ret void
 }
 
 ; Directly map an alloca's address.
 ;
 ; Callsite 16
 ; CHECK-LABEL:  .long L{{.*}}-_directFrameIdx
 ; CHECK-NEXT:   .short 0
 ; 1 location
 ; CHECK-NEXT:   .short  1
 ; Loc 0: Direct RBP - ofs
 ; CHECK-NEXT:   .byte 2
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  6
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long
 
 define void @directFrameIdx() {
 entry:
   %metadata1 = alloca i64, i32 3, align 8
   store i64 11, i64* %metadata1
   store i64 12, i64* %metadata1
   store i64 13, i64* %metadata1

llvm/trunk/test/CodeGen/X86/stackmap-large-constants.ll

 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
 
 ; CHECK-LABEL:  .section  __LLVM_STACKMAPS,__llvm_stackmaps
 ; CHECK-NEXT: __LLVM_StackMaps:
 ; version
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; reserved
 ; CHECK-NEXT:   .byte 0
 ; reserved
 ; CHECK-NEXT:   .short  0
 ; # functions
 ; CHECK-NEXT:   .long 2
 ; # constants
 ; CHECK-NEXT:   .long 2

 ; CHECK-NEXT:   .long L{{.*}}-_foo
 ; reserved
 ; CHECK-NEXT:   .short  0
 ; # locations
 ; CHECK-NEXT:   .short  1
 ; ConstantIndex
 ; CHECK-NEXT:   .byte 5
 ; reserved
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; size
+; CHECK-NEXT:   .short  8
 ; Dwarf RegNum
 ; CHECK-NEXT:   .short  0
+; reserved
+; CHECK-NEXT:   .short  0
 ; Offset
 ; CHECK-NEXT:   .long 0
 ; padding
+; CHECK-NEXT:   .p2align 3
 ; CHECK-NEXT:   .short  0
 ; NumLiveOuts
 ; CHECK-NEXT:   .short  0
 
 ; CHECK-NEXT:   .p2align  3
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
 
 define void @foo() {
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 0, i64 9223372036854775807)
   ret void
 }
 
 ; Patchpoint ID
 ; CHECK-NEXT:   .quad 0
 ; Instruction Offset
 ; CHECK-NEXT:   .long L{{.*}}-_bar
 ; reserved
 ; CHECK-NEXT:   .short  0
 ; # locations
 ; CHECK-NEXT:   .short  1
 ; ConstantIndex
 ; CHECK-NEXT:   .byte 5
 ; reserved
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; size
+; CHECK-NEXT:   .short  8
 ; Dwarf RegNum
 ; CHECK-NEXT:   .short  0
+; reserved
+; CHECK-NEXT:    .short 0
 ; Offset
 ; CHECK-NEXT:   .long 1
 ; padding
+; CHECK-NEXT:  .p2align 3
 ; CHECK-NEXT:   .short  0
 ; NumLiveOuts
 ; CHECK-NEXT:   .short  0
 
 
 define void @bar() {
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 0, i64 -9223372036854775808)
   ret void
 }

llvm/trunk/test/CodeGen/X86/stackmap-large-location-size.ll

+; RUN: llc < %s -mtriple="x86_64-pc-linux-gnu" | FileCheck %s
+
+declare void @callee()
+
+define void @f_0(<1024 x i64> %val) {
+; CHECK:      .quad 2882400015
+; CHECK-NEXT: .long .Ltmp0-f_0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  4
+; Constant(0)
+; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0 
+; CHECK-NEXT: .short  8
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Constant(0)
+; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Constant(1)
+; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 1
+; Indirect
+; CHECK-NEXT: .byte 3
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8192
+; CHECK-NEXT: .short  7
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Padding
+; CHECK-NEXT: .p2align  3
+  call void @callee() [ "deopt"(<1024 x i64> %val) ]
+  ret void
+}
+
+define void @f_1(<1024 x i8*> %val) {
+; CHECK:      .quad 2882400015
+; CHECK-NEXT: .long .Ltmp1-f_1
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  4
+; Constant(0)
+; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Constant(0)
+; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Constant(1)
+; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 1
+; Indirect
+; CHECK-NEXT: .byte 3
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8192
+; CHECK-NEXT: .short  7
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Padding
+; CHECK-NEXT: .p2align  3
+  call void @callee() [ "deopt"(<1024 x i8*> %val) ]
+  ret void
+}
+
+define void @f_2(<99 x i8*> %val) {
+; CHECK:      .quad 2882400015
+; CHECK-NEXT: .long .Ltmp2-f_2
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  4
+; Constant(0)
+; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Constant(0)
+; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Constant(1)
+; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 1
+; Indirect
+; CHECK-NEXT: .byte 3
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  792
+; CHECK-NEXT: .short  7
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; CHECK-NEXT: .p2align  3
+  call void @callee() [ "deopt"(<99 x i8*> %val) ]
+  ret void
+}
+
+
+define <400 x i8 addrspace(1)*> @f_3(<400 x i8 addrspace(1)*> %obj) gc "statepoint-example" {
+; CHECK:      .quad 4242
+; CHECK-NEXT: .long .Ltmp3-f_3
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  5
+; Constant(0)
+; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Constant(0)
+; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Constant(0)
+; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  8
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Indirect
+; CHECK-NEXT: .byte 3
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  3200
+; CHECK-NEXT: .short  7
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Indirect
+; CHECK-NEXT: .byte 3
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short  3200
+; CHECK-NEXT: .short  7
+; CHECK-NEXT: .short  0
+; CHECK-NEXT: .long 0
+; Padding
+; CHECK-NEXT: .p2align  3
+  %tok = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 4242, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0, <400 x i8 addrspace(1)*> %obj)
+  %obj.r = call coldcc <400 x i8 addrspace(1)*> @llvm.experimental.gc.relocate.v400p1i8(token %tok, i32 7, i32 7)
+  ret <400 x i8 addrspace(1)*> %obj.r
+}
+
+declare void @do_safepoint()
+
+declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+declare <400 x i8 addrspace(1)*> @llvm.experimental.gc.relocate.v400p1i8(token, i32, i32)

llvm/trunk/test/CodeGen/X86/stackmap-liveness.ll

 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -enable-patchpoint-liveness=false | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx                                   | FileCheck -check-prefix=PATCH %s
 ;
 ; Note: Print verbose stackmaps using -debug-only=stackmaps.
 
 ; CHECK-LABEL:  .section  __LLVM_STACKMAPS,__llvm_stackmaps
 ; CHECK-NEXT:   __LLVM_StackMaps:
 ; Header
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
 ; CHECK-NEXT:   .long 2
 ; Num LargeConstants
 ; CHECK-NEXT:   .long   0
 ; Num Callsites
 ; CHECK-NEXT:   .long   5

 define void @stackmap_liveness() {
 entry:
   %a1 = call <2 x double> asm sideeffect "", "={xmm2}"() nounwind
 ; StackMap 1 (no liveness information available)
 ; CHECK-LABEL:  .long L{{.*}}-_stackmap_liveness
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; Padding
+; CHECK-NEXT:   .p2align 3
 ; CHECK-NEXT:   .short  0
 ; Num LiveOut Entries: 0
 ; CHECK-NEXT:   .short  0
 ; Align
 ; CHECK-NEXT:   .p2align  3
 
 ; StackMap 1 (patchpoint liveness information enabled)
 ; PATCH-LABEL:  .long L{{.*}}-_stackmap_liveness
 ; PATCH-NEXT:   .short  0
 ; PATCH-NEXT:   .short  0
 ; Padding
+; PATCH-NEXT:   .p2align  3
 ; PATCH-NEXT:   .short  0
 ; Num LiveOut Entries: 1
 ; PATCH-NEXT:   .short  1
 ; LiveOut Entry 1: %YMM2 (16 bytes) --> %XMM2
 ; PATCH-NEXT:   .short  19
 ; PATCH-NEXT:   .byte 0
 ; PATCH-NEXT:   .byte 16
 ; Align
 ; PATCH-NEXT:   .p2align  3
   call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 12, i8* null, i32 0)
   %a2 = call i64 asm sideeffect "", "={r8}"() nounwind
   %a3 = call i8 asm sideeffect "", "={ah}"() nounwind
   %a4 = call <4 x double> asm sideeffect "", "={ymm0}"() nounwind
   %a5 = call <4 x double> asm sideeffect "", "={ymm1}"() nounwind
 
 ; StackMap 2 (no liveness information available)
 ; CHECK-LABEL:  .long L{{.*}}-_stackmap_liveness
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; Padding
+; CHECK-NEXT:   .p2align  3
 ; CHECK-NEXT:   .short  0
 ; Num LiveOut Entries: 0
 ; CHECK-NEXT:   .short  0
 ; Align
 ; CHECK-NEXT:   .p2align  3
 
 ; StackMap 2 (patchpoint liveness information enabled)
 ; PATCH-LABEL:  .long L{{.*}}-_stackmap_liveness
 ; PATCH-NEXT:   .short  0
 ; PATCH-NEXT:   .short  0
 ; Padding
+; PATCH-NEXT:   .p2align  3
 ; PATCH-NEXT:   .short  0
 ; Num LiveOut Entries: 5
 ; PATCH-NEXT:   .short  5
 ; LiveOut Entry 1: %RAX (1 bytes) --> %AL or %AH
 ; PATCH-NEXT:   .short  0
 ; PATCH-NEXT:   .byte 0
 ; PATCH-NEXT:   .byte 1
 ; LiveOut Entry 2: %R8 (8 bytes)
; PATCH-NEXT:   .p2align  3
   call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 2, i32 12, i8* null, i32 0)
   call void asm sideeffect "", "{r8},{ah},{ymm0},{ymm1}"(i64 %a2, i8 %a3, <4 x double> %a4, <4 x double> %a5) nounwind
 
 ; StackMap 3 (no liveness information available)
 ; CHECK-LABEL:  .long L{{.*}}-_stackmap_liveness
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; Padding
+; CHECK-NEXT:   .p2align  3
 ; CHECK-NEXT:   .short  0
 ; Num LiveOut Entries: 0
 ; CHECK-NEXT:   .short  0
 ; Align
 ; CHECK-NEXT:   .p2align  3
 
 ; StackMap 3 (patchpoint liveness information enabled)
 ; PATCH-LABEL:  .long L{{.*}}-_stackmap_liveness
 ; PATCH-NEXT:   .short  0
 ; PATCH-NEXT:   .short  0
 ; Padding
+; PATCH-NEXT:   .p2align  3
 ; PATCH-NEXT:   .short  0
 ; Num LiveOut Entries: 2
 ; PATCH-NEXT:   .short  2
 ; LiveOut Entry 1: %RSP (8 bytes)
 ; PATCH-NEXT:   .short  7
 ; PATCH-NEXT:   .byte 0
 ; PATCH-NEXT:   .byte 8
 ; LiveOut Entry 2: %YMM2 (16 bytes) --> %XMM2

 define void @mixed_liveness() {
 entry:
   %a1 = call <2 x double> asm sideeffect "", "={xmm2}"() nounwind
 ; StackMap 4 (patchpoint liveness information enabled)
 ; PATCH-LABEL:  .long L{{.*}}-_mixed_liveness
 ; PATCH-NEXT:   .short  0
 ; PATCH-NEXT:   .short  0
 ; Padding
+; PATCH-NEXT:   .p2align  3
 ; PATCH-NEXT:   .short  0
 ; Num LiveOut Entries: 0
 ; PATCH-NEXT:   .short  0
 ; Align
 ; PATCH-NEXT:   .p2align  3
 
 ; StackMap 5 (patchpoint liveness information enabled)
 ; PATCH-LABEL:  .long L{{.*}}-_mixed_liveness
 ; PATCH-NEXT:   .short  0
 ; PATCH-NEXT:   .short  0
 ; Padding
+; PATCH-NEXT:   .p2align  3
 ; PATCH-NEXT:   .short  0
 ; Num LiveOut Entries: 2
 ; PATCH-NEXT:   .short  2
 ; LiveOut Entry 1: %RSP (8 bytes)
 ; PATCH-NEXT:   .short  7
 ; PATCH-NEXT:   .byte 0
 ; PATCH-NEXT:   .byte 8
 ; LiveOut Entry 2: %YMM2 (16 bytes) --> %XMM2

llvm/trunk/test/CodeGen/X86/stackmap.ll

 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s
 ;
 ; Note: Print verbose stackmaps using -debug-only=stackmaps.
 
 ; CHECK-LABEL:  .section  __LLVM_STACKMAPS,__llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
 ; Header
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
 ; CHECK-NEXT:   .long 16
 ; Num LargeConstants
 ; CHECK-NEXT:   .long 3
 ; Num Callsites
 ; CHECK-NEXT:   .long 20

 ; Constant arguments
 ;
 ; CHECK-NEXT:   .quad   1
 ; CHECK-NEXT:   .long   L{{.*}}-_constantargs
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  12
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -1
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -1
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   65536
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   2000000000
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   2147483647
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -1
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -1
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; LargeConstant at index 0
 ; CHECK-NEXT:   .byte   5
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; LargeConstant at index 1
 ; CHECK-NEXT:   .byte   5
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   1
 ; LargeConstant at index 2
 ; CHECK-NEXT:   .byte   5
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   2
 ; SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -1
 
 define void @constantargs() {
 entry:
   %0 = inttoptr i64 12345 to i8*
   tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 15, i8* %0, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1)
   ret void
 }
 
 ; Inline OSR Exit
 ;
 ; CHECK-LABEL:  .long   L{{.*}}-_osrinline
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long  0
 define void @osrinline(i64 %a, i64 %b) {
 entry:
   ; Runtime void->void call.
   call void inttoptr (i64 -559038737 to void ()*)()
   ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
   ret void
 }
 
 ; Cold OSR Exit
 ;
 ; 2 live variables in register.
 ;
 ; CHECK-LABEL:  .long   L{{.*}}-_osrcold
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define void @osrcold(i64 %a, i64 %b) {
 entry:
   %test = icmp slt i64 %a, %b
   br i1 %test, label %ret, label %cold
 cold:
   ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
   %thunk = inttoptr i64 -559038737 to i8*
   call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 15, i8* %thunk, i32 0, i64 %a, i64 %b)
   unreachable
 ret:
   ret void
 }
 
 ; Property Read
 ; CHECK-LABEL:  .long   L{{.*}}-_propertyRead
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define i64 @propertyRead(i64* %obj) {
 entry:
   %resolveRead = inttoptr i64 -559038737 to i8*
   %result = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %resolveRead, i32 1, i64* %obj)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Property Write
 ; CHECK-LABEL:  .long   L{{.*}}-_propertyWrite
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
 entry:
   %resolveWrite = inttoptr i64 -559038737 to i8*
   call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 15, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
   ret void
 }
 
 ; Void JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK-LABEL:  .long   L{{.*}}-_jsVoidCall
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
   %resolveCall = inttoptr i64 -559038737 to i8*
   call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
   ret void
 }
 
 ; i64 JS Call
 ;
 ; 2 live variables in registers.
 ;
 ; CHECK-LABEL:  .long   L{{.*}}-_jsIntCall
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  2
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 ; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  {{[0-9]+}}
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   0
 define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
 entry:
   %resolveCall = inttoptr i64 -559038737 to i8*
   %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
   %add = add i64 %result, 3
   ret i64 %add
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 17 stack map entries.
 ;
 ; CHECK-LABEL:  .long L{{.*}}-_spilledValue
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 17
 ;
 ; Check that at least one is a spilled entry from RBP.
 ; Location: Indirect RBP + ...
 ; CHECK:        .byte 3
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short 6
+; CHECK-NEXT:   .short 0
+; CHECK-NEXT:   .long
 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
 entry:
   call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 15, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
   ret void
 }
 
 ; Spilled stack map values.
 ;
 ; Verify 17 stack map entries.
 ;
 ; CHECK-LABEL:  .long L{{.*}}-_spilledStackMapValue
 ; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .short 17
 ;
 ; Check that at least one is a spilled entry from RBP.
 ; Location: Indirect RBP + ...
 ; CHECK:        .byte 3
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short 8
 ; CHECK-NEXT:   .short 6
+; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .long
 define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
 entry:
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 15, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
   ret void
 }
 
 ; Spill a subregister stackmap operand.
 ;
 ; CHECK-LABEL:  .long L{{.*}}-_spillSubReg
 ; CHECK-NEXT:   .short 0
 ; 4 locations
 ; CHECK-NEXT:   .short 1
 ;
 ; Check that the subregister operand is a 4-byte spill.
 ; Location: Indirect, 4-byte, RBP + ...
 ; CHECK:        .byte 3
-; CHECK-NEXT:   .byte 4
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 4
 ; CHECK-NEXT:   .short 6
+; CHECK-NEXT:   .short 0
+; CHECK-NEXT:   .long
 define void @spillSubReg(i64 %arg) #0 {
 bb:
   br i1 undef, label %bb1, label %bb2
 
 bb1:
   unreachable
 
 bb2:

 ; CHECK-LABEL:  .long L{{.*}}-_subRegOffset
 ; CHECK-NEXT:   .short 0
 ; 2 locations
 ; CHECK-NEXT:   .short 2
 ;
 ; Check that the subregister operands are 1-byte spills.
 ; Location 0: Register, 4-byte, AL
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .short 0
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short 1
+; CHECK-NEXT:   .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long 0
 ;
 ; Location 1: Register, 4-byte, BL
 ; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 1
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 1
 ; CHECK-NEXT:   .short 3
+; CHECK-NEXT:   .short 0
 ; CHECK-NEXT:   .long 0
 define void @subRegOffset(i16 %arg) {
   %v = mul i16 %arg, 5
   %a0 = trunc i16 %v to i8
   tail call void asm sideeffect "nop", "~{bx}"() nounwind
   %arghi = lshr i16 %v, 8
   %a1 = trunc i16 %arghi to i8
   tail call void asm sideeffect "nop", "~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 5, i8 %a0, i8 %a1)
   ret void
 }
 
 ; Map a constant value.
 ;
 ; CHECK-LABEL:  .long L{{.*}}-_liveConstant
 ; CHECK-NEXT:   .short 0
 ; 1 location
 ; CHECK-NEXT:   .short 1
 ; Loc 0: SmallConstant
 ; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   33
 
 define void @liveConstant() {
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 5, i32 33)
   ret void
 }
 
 ; Directly map an alloca's address.
 ;
 ; Callsite 16
 ; CHECK-LABEL:  .long L{{.*}}-_directFrameIdx
 ; CHECK-NEXT:   .short 0
 ; 1 location
 ; CHECK-NEXT:   .short  1
 ; Loc 0: Direct RBP - ofs
 ; CHECK-NEXT:   .byte 2
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  6
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long
 
 ; Callsite 17
 ; CHECK-LABEL:  .long L{{.*}}-_directFrameIdx
 ; CHECK-NEXT:   .short  0
 ; 2 locations
 ; CHECK-NEXT:   .short  2
 ; Loc 0: Direct RBP - ofs
 ; CHECK-NEXT:   .byte 2
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  6
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long
 ; Loc 1: Direct RBP - ofs
 ; CHECK-NEXT:   .byte 2
-; CHECK-NEXT:   .byte 8
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  8
 ; CHECK-NEXT:   .short  6
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long
 define void @directFrameIdx() {
 entry:
   %metadata1 = alloca i64, i32 3, align 8
   store i64 11, i64* %metadata1
   store i64 12, i64* %metadata1
   store i64 13, i64* %metadata1
   call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 0, i64* %metadata1)

 ; The scratch register should not be used for a live stackmap value.
 ;
 ; CHECK-LABEL:  .long L{{.*}}-_clobberScratch
 ; CHECK-NEXT:   .short 0
 ; 1 location
 ; CHECK-NEXT:   .short 1
 ; Loc 0: Indirect fp - offset
 ; CHECK-NEXT:   .byte   3
-; CHECK-NEXT:   .byte   4
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT:   .short  4
 ; CHECK-NEXT:   .short  6
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT:   .long   -{{[0-9]+}}
 define void @clobberScratch(i32 %a) {
   tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r12},~{r13},~{r14},~{r15}"() nounwind
   tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
   ret void
 }
 
 ; A stack frame which needs to be realigned at runtime (to meet alignment 

llvm/trunk/test/CodeGen/X86/statepoint-allocas.ll

 }
 
 declare token @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i32, ...)
 
 
 ; CHECK-LABEL: .section .llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
 ; Header
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
 ; CHECK-NEXT:   .long 2
 ; Num LargeConstants
 ; CHECK-NEXT:   .long 0
 ; Num Callsites
 ; CHECK-NEXT:   .long 2

 
 ; Callsites
 ; The GC one
 ; CHECK: .long  .Ltmp0-test
 ; CHECK: .short 0
 ; CHECK: .short 4
 ; SmallConstant (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK: .byte  0
+; CHECK: .short 8
+; CHECK: .short 0
 ; CHECK: .short 0
 ; CHECK: .long  0
 ; SmallConstant (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK: .byte  0
+; CHECK: .short 8
+; CHECK: .short 0
 ; CHECK: .short 0
 ; CHECK: .long  0
 ; SmallConstant (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK: .byte  0
+; CHECK: .short 8
+; CHECK: .short 0
 ; CHECK: .short 0
 ; CHECK: .long  0
 ; Direct Spill Slot [RSP+0]
 ; CHECK: .byte  2
-; CHECK: .byte  8
+; CHECK: .byte  0
+; CHECK: .short 8
 ; CHECK: .short 7
+; CHECK: .short 0
 ; CHECK: .long  0
 ; No Padding or LiveOuts
 ; CHECK: .short 0
 ; CHECK: .short 0
 ; CHECK: .p2align 3
 
 ; The Deopt one
 ; CHECK: .long  .Ltmp1-test2
 ; CHECK: .short 0
 ; CHECK: .short 4
 ; SmallConstant (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK: .byte  0
+; CHECK: .short 8
+; CHECK: .short 0
 ; CHECK: .short 0
 ; CHECK: .long  0
 ; SmallConstant (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK: .byte  0
+; CHECK: .short 8
+; CHECK: .short 0
 ; CHECK: .short 0
 ; CHECK: .long  0
 ; SmallConstant (1)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK: .byte  0
+; CHECK: .short 8
+; CHECK: .short 0
 ; CHECK: .short 0
 ; CHECK: .long  1
 ; Direct Spill Slot [RSP+0]
 ; CHECK: .byte  2
-; CHECK: .byte  8
+; CHECK: .byte  0
+; CHECK: .short 8
 ; CHECK: .short 7
+; CHECK: .short 0
 ; CHECK: .long  0
 
 ; No Padding or LiveOuts
 ; CHECK: .short 0
 ; CHECK: .short 0
 ; CHECK: .p2align 3

llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll

; CHECK-NEXT:   callq _bar
   call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @baz, i32 0, i32 0, i32 0, i32 1, i32 %a)
   call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a)
   ret void
 }
 
 
 ; CHECK: Ltmp0-_test1
 ; CHECK:      .byte 1
-; CHECK-NEXT: .byte 4
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT: .short 4
 ; CHECK-NEXT: .short  5
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT: .long 0
 
 ; CHECK: Ltmp1-_test2
 ; CHECK:      .byte 1
-; CHECK-NEXT: .byte 4
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT: .short 4
 ; CHECK-NEXT: .short  6
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT: .long 0
 ; CHECK:      .byte 1
-; CHECK-NEXT: .byte 4
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT: .short 4
 ; CHECK-NEXT: .short  3
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT: .long 0
 ; CHECK: Ltmp2-_test2
 ; CHECK:      .byte 1
-; CHECK-NEXT: .byte 4
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT: .short 4
 ; CHECK-NEXT: .short  3
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT: .long 0
 ; CHECK:      .byte 1
-; CHECK-NEXT: .byte 4
+; CHECK-NEXT:   .byte   0
+; CHECK-NEXT: .short 4
 ; CHECK-NEXT: .short  6
+; CHECK-NEXT:   .short  0
 ; CHECK-NEXT: .long 0
 
 declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
 declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token, i32, i32)
 
 
 attributes #0 = { "deopt-lowering"="live-in" }
 attributes #1 = { "deopt-lowering"="live-through" }

llvm/trunk/test/CodeGen/X86/statepoint-stackmap-format.ll

 
 declare token @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i32, ...)
 declare i1 @llvm.experimental.gc.result.i1(token)
 declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token, i32, i32) #3
 
 ; CHECK-LABEL: .section .llvm_stackmaps
 ; CHECK-NEXT:  __LLVM_StackMaps:
 ; Header
-; CHECK-NEXT:   .byte 2
+; CHECK-NEXT:   .byte 3
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
 ; CHECK-NEXT:   .long 3
 ; Num LargeConstants
 ; CHECK-NEXT:   .long 0
 ; Num Callsites
 ; CHECK-NEXT:   .long 3

 
 ; Callsites
 ; Constant arguments
 ; CHECK-NEXT: .long .Ltmp0-test
 ; CHECK: .short 0
 ; CHECK: .short 11
 ; SmallConstant (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  0
 ; SmallConstant (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  0
 ; SmallConstant (2)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  2
 ; Indirect Spill Slot [RSP+0]
 ; CHECK: .byte  3
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 7
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  16
 ; SmallConstant  (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  0
 ; SmallConstant  (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  0
 ; SmallConstant  (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  0
 ; Indirect Spill Slot [RSP+16]
 ; CHECK: .byte  3
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 7
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  16
 ; Indirect Spill Slot [RSP+8]
 ; CHECK: .byte  3
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 7
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  8
 ; Indirect Spill Slot [RSP+16]
 ; CHECK: .byte  3
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 7
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  16
 ; Indirect Spill Slot [RSP+16]
 ; CHECK: .byte  3
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 7
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  16
 
 ; No Padding or LiveOuts
 ; CHECK: .short 0
 ; CHECK: .short 0
 ; CHECK: .p2align 3
 
 ;
 ; test_derived_arg
 
 ; Statepoint ID
 ; CHECK-NEXT: .quad 0
 
 ; Callsites
 ; Constant arguments
 ; CHECK-NEXT: .long .Ltmp1-test_derived_arg
 ; CHECK: .short 0
 ; CHECK: .short 11
 ; SmallConstant (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  0
 ; SmallConstant (2)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  2
 ; Indirect Spill Slot [RSP+0]
 ; CHECK: .byte  3
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 7
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  16
 ; SmallConstant  (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  0
 ; SmallConstant  (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  0
 ; SmallConstant  (0)
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  0
 ; Indirect Spill Slot [RSP+16]
 ; CHECK: .byte  3
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 7
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  16
 ; Indirect Spill Slot [RSP+8]
 ; CHECK: .byte  3
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 7
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  8
 ; Indirect Spill Slot [RSP+16]
 ; CHECK: .byte  3
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 7
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  16
 ; Indirect Spill Slot [RSP+16]
 ; CHECK: .byte  3
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 7
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  16
 
 ; No Padding or LiveOuts
 ; CHECK: .short 0
 ; CHECK: .short 0
 ; CHECK: .p2align 3
 
 ; Records for the test_id function:
 
 ; The Statepoint ID:
 ; CHECK-NEXT: .quad 237
 
 ; Instruction Offset
 ; CHECK-NEXT: .long .Ltmp2-test_id
 
 ; Reserved:
 ; CHECK: .short 0
 
 ; NumLocations:
 ; CHECK: .short 3
 
 ; StkMapRecord[0]:
 ; SmallConstant(0):
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  0
 
 ; StkMapRecord[1]:
 ; SmallConstant(0):
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  0
 
 ; StkMapRecord[2]:
 ; SmallConstant(0):
 ; CHECK: .byte  4
-; CHECK: .byte  8
+; CHECK-NEXT:   .byte   0
+; CHECK: .short 8
 ; CHECK: .short 0
+; CHECK-NEXT:   .short  0
 ; CHECK: .long  0
 
 ; No padding or LiveOuts
 ; CHECK: .short 0
 ; CHECK: .short 0
 ; CHECK: .p2align 3

llvm/trunk/test/CodeGen/X86/statepoint-vector.ll

; CHECK: pop
   %safepoint_token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 1, i128 0)
   ret void
 }
 
 ; CHECK: __LLVM_StackMaps:
 
 ; CHECK: .Ltmp0-test
 ; Check for the two spill slots
-; Stack Maps:     Loc 3: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0]
-; Stack Maps:     Loc 4: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0]
+; Stack Maps:     Loc 3: Indirect 7+0 [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 0]
+; Stack Maps:     Loc 4: Indirect 7+0 [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 0]
 ; CHECK: .byte  3
-; CHECK: .byte  16
+; CHECK: .byte  0
+; CHECK: .short 16
 ; CHECK: .short 7
+; CHECK: .short 0
 ; CHECK: .long  0
 ; CHECK: .byte  3
-; CHECK: .byte  16
+; CHECK: .byte  0
+; CHECK: .short 16
 ; CHECK: .short 7
+; CHECK: .short 0
 ; CHECK: .long  0
 
 ; CHECK: .Ltmp1-test2
 ; Check for the two spill slots
-; Stack Maps:     Loc 3: Indirect 7+16  [encoding: .byte 3, .byte 16, .short 7, .int 16]
-; Stack Maps:     Loc 4: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0]
+; Stack Maps:     Loc 3: Indirect 7+16  [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 16]
+; Stack Maps:     Loc 4: Indirect 7+0 [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 0]
 ; CHECK: .byte  3
-; CHECK: .byte  16
+; CHECK: .byte  0
+; CHECK: .short 16
 ; CHECK: .short 7
+; CHECK: .short 0
 ; CHECK: .long  16
 ; CHECK: .byte  3
-; CHECK: .byte  16
+; CHECK: .byte  0
+; CHECK: .short 16
 ; CHECK: .short 7
+; CHECK: .short 0
 ; CHECK: .long  0
 
 ; CHECK: .Ltmp2-test3
 ; Check for the four spill slots
-; Stack Maps:     Loc 3: Indirect 7+16  [encoding: .byte 3, .byte 16, .short 7, .int 16]
-; Stack Maps:     Loc 4: Indirect 7+16  [encoding: .byte 3, .byte 16, .short 7, .int 16]
-; Stack Maps:     Loc 5: Indirect 7+16  [encoding: .byte 3, .byte 16, .short 7, .int 16]
-; Stack Maps:     Loc 6: Indirect 7+0   [encoding: .byte 3, .byte 16, .short 7, .int 0]
+; Stack Maps:     Loc 3: Indirect 7+16  [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 16]
+; Stack Maps:     Loc 4: Indirect 7+16  [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 16]
+; Stack Maps:     Loc 5: Indirect 7+16  [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 16]
+; Stack Maps:     Loc 6: Indirect 7+0 [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 0]
 ; CHECK: .byte  3
-; CHECK: .byte  16
+; CHECK: .byte  0
+; CHECK: .short 16
 ; CHECK: .short 7
+; CHECK: .short 0
 ; CHECK: .long  16
 ; CHECK: .byte  3
-; CHECK: .byte  16
+; CHECK: .byte   0
+; CHECK: .short 16
 ; CHECK: .short 7
+; CHECK: .short 0
 ; CHECK: .long  16
 ; CHECK: .byte  3
-; CHECK: .byte  16
+; CHECK: .byte   0
+; CHECK: .short 16
 ; CHECK: .short 7
+; CHECK: .short 0
 ; CHECK: .long  16
 ; CHECK: .byte  3
-; CHECK: .byte  16
+; CHECK: .byte   0
+; CHECK: .short 16
 ; CHECK: .short 7
+; CHECK: .short 0
 ; CHECK: .long  0
 
 declare void @do_safepoint()
 
 declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
 declare i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(token, i32, i32)
 declare <2 x i8 addrspace(1)*> @llvm.experimental.gc.relocate.v2p1i8(token, i32, i32)