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Differential D32356

AMDGPU: Fix S_PACK_HH_B32_B16
ClosedPublic

Authored by kzhuravl on Apr 21 2017, 9:10 AM.

Details

Reviewers
arsenm
Commits
rGb93c2f2a0962: AMDGPU: Fix S_PACK_HH_B32_B16 - We really ought to zero out lower 16 bits
rG88938d4e673b: AMDGPU: Fix S_PACK_HH_B32_B16 - We really ought to zero out lower 16 bits
rL301026: AMDGPU: Fix S_PACK_HH_B32_B16
Summary

We really ought to zero out lower 16 bits

Diff Detail

Repository
rL LLVM

Event Timeline

kzhuravl created this revision.Apr 21 2017, 9:10 AM
Herald added subscribers: t-tye, tpr, dstuttard and 3 others. · View Herald TranscriptApr 21 2017, 9:10 AM
kzhuravl updated this revision to Diff 96161.Apr 21 2017, 9:53 AM

Upload full diff.

arsenm accepted this revision.Apr 21 2017, 10:31 AM

LGTM

This revision is now accepted and ready to land.Apr 21 2017, 10:31 AM
Closed by commit rL301026: AMDGPU: Fix S_PACK_HH_B32_B16 (authored by kzhuravl). · Explain WhyApr 21 2017, 12:48 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
2 lines

Diff 96209

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

Show First 20 Lines • Show All 3,589 Lines • ▼ Show 20 Linesvoid SIInstrInfo::movePackToVALU(SmallVectorImpl<MachineInstr *> &Worklist,
} }
case AMDGPU::S_PACK_HH_B32_B16: { case AMDGPU::S_PACK_HH_B32_B16: {
unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg) BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg)
.addImm(16) .addImm(16)
.add(Src0); .add(Src0);
BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
.addImm(0xffff); .addImm(0xffff0000);
BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_OR_B32), ResultReg) BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_OR_B32), ResultReg)
.add(Src1) .add(Src1)
.addReg(ImmReg, RegState::Kill) .addReg(ImmReg, RegState::Kill)
.addReg(TmpReg, RegState::Kill); .addReg(TmpReg, RegState::Kill);
break; break;
} }
default: default:
llvm_unreachable("unhandled s_pack_* instruction"); llvm_unreachable("unhandled s_pack_* instruction");
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llvm/trunk/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll

Show First 20 Lines • Show All 210 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}v_insertelement_v2i16_0_reghi: ; GCN-LABEL: {{^}}v_insertelement_v2i16_0_reghi:
; GCN-DAG: flat_load_dword [[VEC:v[0-9]+]] ; GCN-DAG: flat_load_dword [[VEC:v[0-9]+]]
; GCN-DAG: s_load_dword [[ELT0:s[0-9]+]] ; GCN-DAG: s_load_dword [[ELT0:s[0-9]+]]
; CIVI-DAG: s_lshr_b32 [[ELT0_SHIFT:s[0-9]+]], [[ELT0]], 16 ; CIVI-DAG: s_lshr_b32 [[ELT0_SHIFT:s[0-9]+]], [[ELT0]], 16
; CIVI-DAG: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]] ; CIVI-DAG: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]]
; CIVI: v_or_b32_e32 [[RES:v[0-9]+]], [[ELT0_SHIFT]], [[ELT1]] ; CIVI: v_or_b32_e32 [[RES:v[0-9]+]], [[ELT0_SHIFT]], [[ELT1]]
; GFX9-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff{{$}} ; GFX9-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff0000{{$}}
; GFX9-DAG: v_lshrrev_b32_e64 [[ELT0_SHIFT:v[0-9]+]], 16, [[ELT0]] ; GFX9-DAG: v_lshrrev_b32_e64 [[ELT0_SHIFT:v[0-9]+]], 16, [[ELT0]]
; GFX9: v_and_or_b32 [[RES:v[0-9]+]], [[VEC]], [[MASK]], [[ELT0_SHIFT]] ; GFX9: v_and_or_b32 [[RES:v[0-9]+]], [[VEC]], [[MASK]], [[ELT0_SHIFT]]
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]]
define amdgpu_kernel void @v_insertelement_v2i16_0_reghi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, i32 %elt.arg) #0 { define amdgpu_kernel void @v_insertelement_v2i16_0_reghi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, i32 %elt.arg) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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