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AMDGPU: Move v_readlane lane select from VGPR to SGPR
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Authored by nhaehnle on Apr 21 2017, 2:21 AM.

Details

Summary

Fix a compiler bug when the lane select happens to end up in a VGPR.

Clarify the semantic of the corresponding intrinsic to be that of
the corresponding GLSL: the lane select must be uniform across a
wave front, otherwise results are undefined.

Diff Detail

Repository
rL LLVM

Event Timeline

nhaehnle created this revision.Apr 21 2017, 2:21 AM
arsenm added inline comments.Apr 21 2017, 11:57 AM
lib/Target/AMDGPU/SIInstrInfo.cpp
2639 ↗(On Diff #96111)

Also mention the source is assumed to be uniform?

2642 ↗(On Diff #96111)

SReg32_XM0

2643 ↗(On Diff #96111)

const reference

test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
26 ↗(On Diff #96111)

Can you add a GEP on workitem ID to ensure the scalar load optimization won't ever trigger on this

nhaehnle updated this revision to Diff 96412.Apr 24 2017, 10:04 AM

Address review comments.

arsenm accepted this revision.Apr 24 2017, 10:27 AM

LGTM

This revision is now accepted and ready to land.Apr 24 2017, 10:27 AM
This revision was automatically updated to reflect the committed changes.