[ARM] Modify THREAD_POINTER lowering

[samparker]

Summary

The current implementation of lowering the thread_pointer intrinsic and ARM's THREAD_POINTER node requires the destination register to be hard-coded in tablegen, which does not seem right to me. I've now changed the ARMthread_pointer node to be purely part of a chain, with the i32 value now being produced by a CopyFromReg from R0. The TPsoft and tTPsoft instructions already add R0 to be one of the implicitly defined registers, as this is the register used to hold the return value of __aeabi_read_tp. The tests have been modified because this implementation allows the call to be slightly reordered.

[samparker]

Hi @compnerd and @dblaikie , would you guys mind taking a look at this? I mainly want to check that the reordering of the call is okay.

Cheers,
sam

lib/Target/ARM/ARMExpandPseudoInsts.cpp

       MachineInstrBuilder MIB;
       if (STI->genLongCalls()) {
         MachineFunction *MF = MBB.getParent();
         MachineConstantPool *MCP = MF->getConstantPool();
         unsigned PCLabelID = AFI->createPICLabelUId();
         MachineConstantPoolValue *CPV =
             ARMConstantPoolSymbol::Create(MF->getFunction()->getContext(),
                                           "__aeabi_read_tp", PCLabelID, 0);
-        unsigned Reg = MI.getOperand(0).getReg();
+        unsigned Reg = ARM::R0;
         MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
                       TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
                   .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
         if (!Thumb)
           MIB.addImm(0);
         MIB.add(predOps(ARMCC::AL));
 
         MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),

lib/Target/ARM/ARMISelLowering.cpp

 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
                                         SelectionDAG &DAG,
                                         TLSModel::Model model) const {
   const GlobalValue *GV = GA->getGlobal();
   SDLoc dl(GA);
   SDValue Offset;
   SDValue Chain = DAG.getEntryNode();
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
-  // Get the Thread Pointer
-  SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
 
   if (model == TLSModel::InitialExec) {
     MachineFunction &MF = DAG.getMachineFunction();
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
     // Initial exec model.
     unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
     ARMConstantPoolValue *CPV =

       ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
     Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
     Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
     Offset = DAG.getLoad(
         PtrVT, dl, Chain, Offset,
         MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
   }
 
+  // Get the Thread Pointer, a call which will return the value into R0.
+  Chain = DAG.getNode(ARMISD::THREAD_POINTER, dl, MVT::Other, Chain);
   // The address of the thread local variable is the add of the thread
   // pointer with the offset of the variable.
-  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
+  SDValue ThreadPointer = DAG.getCopyFromReg(Chain, dl, ARM::R0, PtrVT);
+  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer.getValue(0), Offset);
 }
 
 SDValue
 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
   if (Subtarget->isTargetDarwin())
     return LowerGlobalTLSAddressDarwin(Op, DAG);
 
   if (Subtarget->isTargetWindows())

 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
                                           const ARMSubtarget *Subtarget) const {
   unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
   SDLoc dl(Op);
   switch (IntNo) {
   default: return SDValue();    // Don't custom lower most intrinsics.
   case Intrinsic::thread_pointer: {
     EVT PtrVT = getPointerTy(DAG.getDataLayout());
-    return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
+    SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, MVT::Other,
+                                        DAG.getEntryNode());
+    return DAG.getCopyFromReg(ThreadPointer, dl, ARM::R0, PtrVT);
   }
   case Intrinsic::eh_sjlj_lsda: {
     MachineFunction &MF = DAG.getMachineFunction();
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
     EVT PtrVT = getPointerTy(DAG.getDataLayout());
     SDValue CPAddr;
     bool IsPositionIndependent = isPositionIndependent();

lib/Target/ARM/ARMInstrInfo.td

 
 def SDT_ARMCmp     : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
 def SDT_ARMFCmp    : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>,
                                           SDTCisVT<2, i32>]>;
 
 def SDT_ARMPICAdd  : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
                                           SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
 
-def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
+def SDT_ARMThreadPointer : SDTypeProfile<0, 0, []>;
 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
                                                  SDTCisInt<2>]>;
 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
 def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>;
 
 def SDT_ARMMEMBARRIER     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,

 def ARMrrx           : SDNode<"ARMISD::RRX"     , SDTIntUnaryOp, [SDNPInGlue ]>;
 
 def ARMaddc          : SDNode<"ARMISD::ADDC",  SDTBinaryArithWithFlags,
                               [SDNPCommutative]>;
 def ARMsubc          : SDNode<"ARMISD::SUBC",  SDTBinaryArithWithFlags>;
 def ARMadde          : SDNode<"ARMISD::ADDE",  SDTBinaryArithWithFlagsInOut>;
 def ARMsube          : SDNode<"ARMISD::SUBE",  SDTBinaryArithWithFlagsInOut>;
 
-def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
+def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer,
+                              [SDNPHasChain, SDNPSideEffect]>;
 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
                                SDT_ARMEH_SJLJ_Setjmp,
                                [SDNPHasChain, SDNPSideEffect]>;
 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
                                SDT_ARMEH_SJLJ_Longjmp,
                                [SDNPHasChain, SDNPSideEffect]>;
 def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH",
                                       SDT_ARMEH_SJLJ_SetupDispatch,

 // __aeabi_read_tp preserves the registers r1-r3.
 // This is a pseudo inst so that we can get the encoding right,
 // complete with fixup for the aeabi_read_tp function.
 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
 // is defined in "ARMInstrThumb.td".
 let isCall = 1,
   Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
   def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
-               [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
+               [(ARMthread_pointer)]>, Sched<[WriteBr]>;
 }
 
 //===----------------------------------------------------------------------===//
 // SJLJ Exception handling intrinsics
 //   eh_sjlj_setjmp() is an instruction sequence to store the return
 //   address and save #0 in R0 for the non-longjmp case.
 //   Since by its nature we may be coming from some other function to get
 //   here, and we're using the stack frame for the containing function to

lib/Target/ARM/ARMInstrThumb.td

 // TLS Instructions
 //
 
 // __aeabi_read_tp preserves the registers r1-r3.
 // This is a pseudo inst so that we can get the encoding right,
 // complete with fixup for the aeabi_read_tp function.
 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
-                          [(set R0, ARMthread_pointer)]>,
+                          [(ARMthread_pointer)]>,
                           Sched<[WriteBr]>;
 
 //===----------------------------------------------------------------------===//
 // SJLJ Exception handling intrinsics
 //
 
 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
 // save #0 in R0 for the non-longjmp case.  Since by its nature we may be coming

test/CodeGen/ARM/2010-12-08-tpsoft.ll

bb:                                               ; preds = %entry
   ret i32 %1
 ; ELFASM:         bl  __aeabi_read_tp
 
 
 ; ELFOBJ:      Sections [
 ; ELFOBJ:        Section {
 ; ELFOBJ:          Name: .text
 ; ELFOBJ:          SectionData (
-;;;                  BL __aeabi_read_tp is ---------+
-;;;                                                 V
-; ELFOBJ-NEXT:     0000: 00482DE9 3C009FE5 00109FE7 FEFFFFEB
+;;;                  BL __aeabi_read_tp is +
+;;;                                        V
+; ELFOBJ-NEXT:     0000: 00482DE9 3C109FE5 FEFFFFEB 01109FE7
 
 
 bb1:                                              ; preds = %entry
   %2 = tail call arm_aapcs_vfpcc  i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind
   ret i32 %2
 
 bb2:                                              ; preds = %entry
   ret i32 -1
 }
 
 declare arm_aapcs_vfpcc i32 @foo(i8*)
 
 declare arm_aapcs_vfpcc i32 @bar(i32*)

test/CodeGen/ARM/aeabi-read-tp.ll

 ; RUN: llc -mtriple armv7---eabi -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-SHORT
 ; RUN: llc -mtriple thumbv7---eabi -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-SHORT
 ; RUN: llc -mtriple armv7---eabi -mattr=+long-calls -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-LONG
 ; RUN: llc -mtriple thumbv7---eabi -mattr=+long-calls -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-LONG
 
 @i = thread_local local_unnamed_addr global i32 0, align 4
 
 define i32 @f() local_unnamed_addr {
 entry:
   %0 = load i32, i32* @i, align 4
   ret i32 %0
 }
 
 ; CHECK-LABEL: f:
-; CHECK-SHORT: ldr r1, [[VAR:.LCPI[0-9]+_[0-9]+]]
-; CHECK-SHORT-NEXT: bl __aeabi_read_tp
+; CHECK-SHORT: bl __aeabi_read_tp
+; CHECK-SHORT-NEXT: ldr r1, [[VAR:.LCPI[0-9]+_[0-9]+]]
 ; CHECK-SHORT: [[VAR]]:
 ; CHECK-SHORT-NEXT: .long i(TPOFF)
 
 ; CHECK-LONG: ldr [[REG:r[0-9]+]], [[FUN:.LCPI[0-9]+_[0-9]+]]
-; CHECK-LONG-NEXT: ldr r1, [[VAR:.LCPI[0-9]+_[0-9]+]]
 ; CHECK-LONG-NEXT: blx [[REG]]
+; CHECK-LONG-NEXT: ldr r1, [[VAR:.LCPI[0-9]+_[0-9]+]]
 ; CHECK-LONG: [[VAR]]:
 ; CHECK-LONG-NEXT: .long i(TPOFF)
 ; CHECK-LONG: [[FUN]]:
 ; CHECK-LONG-NEXT: .long __aeabi_read_tp

test/CodeGen/Thumb2/tls2.ll

 ; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi | FileCheck %s -check-prefix=CHECK-NOT-PIC
 ; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC
 
 @i = external thread_local global i32   ; <i32*> [#uses=2]
 
 define i32 @f() {
 entry:
 ; CHECK-NOT-PIC-LABEL: f:
-; CHECK-NOT-PIC: add r0, pc
-; CHECK-NOT-PIC: ldr r1, [r0]
-; CHECK-NOT-PIC: i(GOTTPOFF)
+; CHECK-NOT-PIC: ldr r1, [[LCP:.*]]
+; CHECK-NOT-PIC: bl  __aeabi_read_tp
+; CHECK-NOT-PIC: add r1, pc
+; CHECK-NOT-PIC: ldr r1, [r1]
+; CHECK-NOT-PIC: ldr r0, [r0, r1]
+; CHECK-NOT-PIC: [[LCP]]
+; CHECK-NOT-PIC-NEXT: .L
+; CHECK-NOT-PIC-NEXT: i(GOTTPOFF)
 
 ; CHECK-PIC-LABEL: f:
 ; CHECK-PIC: bl __tls_get_addr
   %tmp1 = load i32, i32* @i    ; <i32> [#uses=1]
   ret i32 %tmp1
 }
 
 define i32* @g() {
 entry:
 ; CHECK-NOT-PIC-LABEL: g:
-; CHECK-NOT-PIC: add r0, pc
-; CHECK-NOT-PIC: ldr r1, [r0]
-; CHECK-NOT-PIC: i(GOTTPOFF)
+; CHECK-NOT-PIC: ldr r1, [[LCP:.*]]
+; CHECK-NOT-PIC: bl  __aeabi_read_tp
+; CHECK-NOT-PIC: add r1, pc
+; CHECK-NOT-PIC: ldr r1, [r1]
+; CHECK-NOT-PIC: add r0, r1
+; CHECK-NOT-PIC: [[LCP]]
+; CHECK-NOT-PIC-NEXT: .L
+; CHECK-NOT-PIC-NEXT: i(GOTTPOFF)
 
 ; CHECK-PIC-LABEL: g:
 ; CHECK-PIC: bl __tls_get_addr
   ret i32* @i
 }

test/CodeGen/Thumb2/tpsoft.ll

bb:                                               ; preds = %entry
   ret i32 %1
 ; ELFASM:         bl  __aeabi_read_tp
 
 
 ; ELFOBJ:      Sections [
 ; ELFOBJ:        Section {
 ; ELFOBJ:          Name: .text
 ; ELFOBJ-LE:          SectionData (
-;;;                  BL __aeabi_read_tp is ---+
-;;;                                           V
-; ELFOBJ-LE-NEXT:     0000: 80B50E48 78440168 FFF7FEFF 40580D28
+;;;                  BL __aeabi_read_tp is -+
+;;;                                         V
+; ELFOBJ-LE-NEXT:     0000: 80B50E49 FFF7FEFF 79440968 40580D28
 ; ELFOBJ-BE:          SectionData (
-;;;                  BL __aeabi_read_tp is ---+
-;;;                                           V
-; ELFOBJ-BE-NEXT:     0000: B580480E 44786801 F7FFFFFE 5840280D
+;;;                  BL __aeabi_read_tp is -+
+;;;                                         V
+; ELFOBJ-BE-NEXT:     0000: B580490E F7FFFFFE 44796809 5840280D
 
 
 bb1:                                              ; preds = %entry
   %2 = tail call arm_aapcs_vfpcc  i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind
   ret i32 %2
 
 bb2:                                              ; preds = %entry
   ret i32 -1
 }
 
 declare arm_aapcs_vfpcc i32 @foo(i8*)
 
 declare arm_aapcs_vfpcc i32 @bar(i32*)