PR32710: Disable using PMADDWD for unsigned short.

[danielcdh]

Summary

PMADDWD can only handle signed short.

[mkuper]

LGTM

[andreadb]

Hi Dehao (and Michael),

Test madd.ll has wrong CHECK-LABEL comments. For example, I see that "label" checks are lower-case. Those should be all upper-case.
I think that those checks are never used in practice.

To avoid problems with FileCheck, I also suggest to add an explicit check line for the 'ret' statement. That way, we know exactly what is the range of instructions where (v)pmaddwd should not appear.

-Andrea

[danielcdh]

In D32236#730855, @andreadb wrote:

Hi Dehao (and Michael),

Test madd.ll has wrong CHECK-LABEL comments. For example, I see that "label" checks are lower-case. Those should be all upper-case.
I think that those checks are never used in practice.

To avoid problems with FileCheck, I also suggest to add an explicit check line for the 'ret' statement. That way, we know exactly what is the range of instructions where (v)pmaddwd should not appear.

-Andrea

Thanks, patch updated.

Dehao

[danielcdh]

update test

[craig.topper]

lib/Target/X86/X86ISelLowering.cpp

34634

Should we check Mode == MULU16 first and save the call if it is?

test/CodeGen/X86/madd.ll

1

Can we you just run utils/update_llc_test_checks.py on this file as an NFC pre-commit? Then use the script on your new test case.

[craig.topper]

Oops. didn't notice this was closed already. But can we run the script over the test now?

[danielcdh]

lib/Target/X86/X86ISelLowering.cpp

34634

We actually need to call canReduceVMulWidth first because it will set the Mode.

test/CodeGen/X86/madd.ll

1

done in r300740. Thanks

lib/Target/X86/X86ISelLowering.cpp

   SDValue Phi = N->getOperand(1);
 
   if (MulOp.getOpcode() != ISD::MUL)
     std::swap(MulOp, Phi);
   if (MulOp.getOpcode() != ISD::MUL)
     return SDValue();
 
   ShrinkMode Mode;
-  if (!canReduceVMulWidth(MulOp.getNode(), DAG, Mode))
+  if (!canReduceVMulWidth(MulOp.getNode(), DAG, Mode) || Mode == MULU16)
     return SDValue();
 
   EVT VT = N->getValueType(0);
 
   unsigned RegSize = 128;
   if (Subtarget.hasBWI())
     RegSize = 512;
   else if (Subtarget.hasAVX2())

test/CodeGen/X86/madd.ll

 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX512
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=AVX512
 
 ;SSE2-label: @_Z10test_shortPsS_i
 ;SSE2:        movdqu
 ;SSE2-NEXT:   movdqu
 ;SSE2-NEXT:   pmaddwd
middle.block:
   %rdx.shuf15 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %bin.rdx16 = add <8 x i32> %bin.rdx, %rdx.shuf15
   %rdx.shuf17 = shufflevector <8 x i32> %bin.rdx16, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %bin.rdx18 = add <8 x i32> %bin.rdx16, %rdx.shuf17
   %13 = extractelement <8 x i32> %bin.rdx18, i32 0
   ret i32 %13
 }
 
+;SSE2-label: @_Z10test_shortPsS_i
+;SSE2-NOT: pmaddwd
+
+;AVX2-label: @_Z10test_shortPsS_i
+;AVX2-NOT: vpmaddwd
+
+;AVX512-label: @_Z10test_shortPsS_i
+;AVX512-NOT: vpmaddwd
+
+define i32 @test_unsigned_short(i16* nocapture readonly, i16* nocapture readonly, i32) local_unnamed_addr #0 {
+entry:
+  %3 = zext i32 %2 to i64
+  br label %vector.body
+
+vector.body:
+  %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
+  %vec.phi = phi <8 x i32> [ %11, %vector.body ], [ zeroinitializer, %entry ]
+  %4 = getelementptr inbounds i16, i16* %0, i64 %index
+  %5 = bitcast i16* %4 to <8 x i16>*
+  %wide.load = load <8 x i16>, <8 x i16>* %5, align 2
+  %6 = zext <8 x i16> %wide.load to <8 x i32>
+  %7 = getelementptr inbounds i16, i16* %1, i64 %index
+  %8 = bitcast i16* %7 to <8 x i16>*
+  %wide.load14 = load <8 x i16>, <8 x i16>* %8, align 2
+  %9 = zext <8 x i16> %wide.load14 to <8 x i32>
+  %10 = mul nsw <8 x i32> %9, %6
+  %11 = add nsw <8 x i32> %10, %vec.phi
+  %index.next = add i64 %index, 8
+  %12 = icmp eq i64 %index.next, %3
+  br i1 %12, label %middle.block, label %vector.body
+
+middle.block:
+  %rdx.shuf = shufflevector <8 x i32> %11, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
+  %bin.rdx = add <8 x i32> %11, %rdx.shuf
+  %rdx.shuf15 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %bin.rdx16 = add <8 x i32> %bin.rdx, %rdx.shuf15
+  %rdx.shuf17 = shufflevector <8 x i32> %bin.rdx16, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %bin.rdx18 = add <8 x i32> %bin.rdx16, %rdx.shuf17
+  %13 = extractelement <8 x i32> %bin.rdx18, i32 0
+  ret i32 %13
+}
+
 ;AVX2-label: @_Z9test_charPcS_i
 ;AVX2:       vpmovsxbw
 ;AVX2-NEXT:  vpmovsxbw
 ;AVX2-NEXT:  vpmaddwd
 ;AVX2-NEXT:  vpaddd
 
 ;AVX512-label: @_Z9test_charPcS_i
 ;AVX512:       vpmovsxbw