[ARM] Add hardware build attributes in assembler

[olista01]

Summary

In the assembler, we should emit build attributes based on the target
selected with command-line options. This matches the GNU assembler's
behaviour. We only do this for build attributes which describe the
hardware that is expected to be available, not the ones that describe
ABI compatibility.

This is done by moving some of the attribute emission code to
ARMTargetStreamer, so that it can be shared between the assembly and
code-generation code paths. Since the assembler only creates a
MCSubtargetInfo, not an ARMSubtarget, the code had to be changed to
check raw features, and not use the convenience functions in
ARMSubtarget.

If different attributes are later specified using the .eabi_attribute
directive, then they will take precedence, as happens when the same
.eabi_attribute is specified twice.

This must be enabled by an option, because we don't want to do this when
parsing inline assembly. The attributes would match the ones emitted at
the start of the file, so wouldn't actually change the emitted object
file, but the extra directives would be added to every inline assembly
block when emitting assembly, which we'd like to avoid.

The majority of the changes in the build-attributes.ll test are just
re-ordering the directives, because the hardware attributes are now
emitted before the ABI ones. However, I did fix one bug which I spotted:
Tag_CPU_arch_profile was not being emitted for v6M.

[olista01]

Ping.

[rengolin]

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

71

Why is this false? Don't we always want to emit the attributes?

[olista01]

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

71

We do want to emit attributes here when assembling an assembly file, but not when parsing inline assembly, so there's no obvious default when using this as part of clang. It's also not important what the default is when driving this from clang, as it doesn't change the final user interface.

When using this as a development/testing tool through llvm-mc, not emitting the build attributes is a sensible default, as you generally don't care about them, so I set this to default to false.

[rengolin]

Makes sense. LGTM. Thanks!

include/llvm/MC/MCStreamer.h

public:
   virtual void emitAttribute(unsigned Attribute, unsigned Value);
   virtual void emitTextAttribute(unsigned Attribute, StringRef String);
   virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
                                     StringRef StringValue = "");
   virtual void emitFPU(unsigned FPU);
   virtual void emitArch(unsigned Arch);
   virtual void emitArchExtension(unsigned ArchExt);
   virtual void emitObjectArch(unsigned Arch);
+  void emitTargetAttributes(const MCSubtargetInfo &STI);
   virtual void finishAttributeSection();
   virtual void emitInst(uint32_t Inst, char Suffix = '\0');
 
   virtual void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE);
 
   virtual void emitThumbSet(MCSymbol *Symbol, const MCExpr *Value);
 
   void finish() override;

include/llvm/MC/MCSubtargetInfo.h

public:
   }
 
   /// setFeatureBits - Set the feature bits.
   ///
   void setFeatureBits(const FeatureBitset &FeatureBits_) {
     FeatureBits = FeatureBits_;
   }
 
+  bool hasFeature(unsigned Feature) const {
+    return FeatureBits[Feature];
+  }
+
 protected:
   /// Initialize the scheduling model and feature bits.
   ///
   /// FIXME: Find a way to stick this in the constructor, since it should only
   /// be called during initialization.
   void InitMCProcessorInfo(StringRef CPU, StringRef FS);
 
 public:

lib/Target/ARM/ARMAsmPrinter.cpp

if (OptimizationGoals > 0 &&
       (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
        Subtarget->isTargetMuslAEABI()))
     ATS.emitAttribute(ARMBuildAttrs::ABI_optimization_goals, OptimizationGoals);
   OptimizationGoals = -1;
 
   ATS.finishAttributeSection();
 }
 
-static bool isV8M(const ARMSubtarget *Subtarget) {
-  // Note that v8M Baseline is a subset of v6T2!
-  return (Subtarget->hasV8MBaselineOps() && !Subtarget->hasV6T2Ops()) ||
-         Subtarget->hasV8MMainlineOps();
-}
-
 //===----------------------------------------------------------------------===//
 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
 // FIXME:
 // The following seem like one-off assembler flags, but they actually need
 // to appear in the .ARM.attributes section in ELF.
 // Instead of subclassing the MCELFStreamer, we do the work here.
 
-static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
-                                            const ARMSubtarget *Subtarget) {
-  if (CPU == "xscale")
-    return ARMBuildAttrs::v5TEJ;
-
-  if (Subtarget->hasV8Ops()) {
-    if (Subtarget->isRClass())
-      return ARMBuildAttrs::v8_R;
-    return ARMBuildAttrs::v8_A;
-  } else if (Subtarget->hasV8MMainlineOps())
-    return ARMBuildAttrs::v8_M_Main;
-  else if (Subtarget->hasV7Ops()) {
-    if (Subtarget->isMClass() && Subtarget->hasDSP())
-      return ARMBuildAttrs::v7E_M;
-    return ARMBuildAttrs::v7;
-  } else if (Subtarget->hasV6T2Ops())
-    return ARMBuildAttrs::v6T2;
-  else if (Subtarget->hasV8MBaselineOps())
-    return ARMBuildAttrs::v8_M_Base;
-  else if (Subtarget->hasV6MOps())
-    return ARMBuildAttrs::v6S_M;
-  else if (Subtarget->hasV6Ops())
-    return ARMBuildAttrs::v6;
-  else if (Subtarget->hasV5TEOps())
-    return ARMBuildAttrs::v5TE;
-  else if (Subtarget->hasV5TOps())
-    return ARMBuildAttrs::v5T;
-  else if (Subtarget->hasV4TOps())
-    return ARMBuildAttrs::v4T;
-  else
-    return ARMBuildAttrs::v4;
-}
-
 // Returns true if all functions have the same function attribute value.
 // It also returns true when the module has no functions.
 static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr,
                                                StringRef Value) {
   return !any_of(M, [&](const Function &F) {
     return F.getFnAttribute(Attr).getValueAsString() != Value;
   });
 }
if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
     else
       ArchFS = FS;
   }
   const ARMBaseTargetMachine &ATM =
       static_cast<const ARMBaseTargetMachine &>(TM);
   const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
 
-  const std::string &CPUString = STI.getCPUString();
-
-  if (!StringRef(CPUString).startswith("generic")) {
-    // FIXME: remove krait check when GNU tools support krait cpu
-    if (STI.isKrait()) {
-      ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
-      // We consider krait as a "cortex-a9" + hwdiv CPU
-      // Enable hwdiv through ".arch_extension idiv"
-      if (STI.hasDivide() || STI.hasDivideInARMMode())
-        ATS.emitArchExtension(ARM::AEK_HWDIV | ARM::AEK_HWDIVARM);
-    } else
-      ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
-  }
-
-  ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
-
-  // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
-  // profile is not applicable (e.g. pre v7, or cross-profile code)".
-  if (STI.hasV7Ops() || isV8M(&STI)) {
-    if (STI.isAClass()) {
-      ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
-                        ARMBuildAttrs::ApplicationProfile);
-    } else if (STI.isRClass()) {
-      ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
-                        ARMBuildAttrs::RealTimeProfile);
-    } else if (STI.isMClass()) {
-      ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
-                        ARMBuildAttrs::MicroControllerProfile);
-    }
-  }
-
-  ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
-                    STI.hasARMOps() ? ARMBuildAttrs::Allowed
-                                    : ARMBuildAttrs::Not_Allowed);
-  if (isV8M(&STI)) {
-    ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
-                      ARMBuildAttrs::AllowThumbDerived);
-  } else if (STI.isThumb1Only()) {
-    ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
-  } else if (STI.hasThumb2()) {
-    ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
-                      ARMBuildAttrs::AllowThumb32);
-  }
-
-  if (STI.hasNEON()) {
-    /* NEON is not exactly a VFP architecture, but GAS emit one of
-     * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
-    if (STI.hasFPARMv8()) {
-      if (STI.hasCrypto())
-        ATS.emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
-      else
-        ATS.emitFPU(ARM::FK_NEON_FP_ARMV8);
-    } else if (STI.hasVFP4())
-      ATS.emitFPU(ARM::FK_NEON_VFPV4);
-    else
-      ATS.emitFPU(STI.hasFP16() ? ARM::FK_NEON_FP16 : ARM::FK_NEON);
-    // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
-    if (STI.hasV8Ops())
-      ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
-                        STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
-                                            ARMBuildAttrs::AllowNeonARMv8);
-  } else {
-    if (STI.hasFPARMv8())
-      // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
-      // FPU, but there are two different names for it depending on the CPU.
-      ATS.emitFPU(STI.hasD16()
-                  ? (STI.isFPOnlySP() ? ARM::FK_FPV5_SP_D16 : ARM::FK_FPV5_D16)
-                  : ARM::FK_FP_ARMV8);
-    else if (STI.hasVFP4())
-      ATS.emitFPU(STI.hasD16()
-                  ? (STI.isFPOnlySP() ? ARM::FK_FPV4_SP_D16 : ARM::FK_VFPV4_D16)
-                  : ARM::FK_VFPV4);
-    else if (STI.hasVFP3())
-      ATS.emitFPU(STI.hasD16()
-                  // +d16
-                  ? (STI.isFPOnlySP()
-                     ? (STI.hasFP16() ? ARM::FK_VFPV3XD_FP16 : ARM::FK_VFPV3XD)
-                     : (STI.hasFP16() ? ARM::FK_VFPV3_D16_FP16 : ARM::FK_VFPV3_D16))
-                  // -d16
-                  : (STI.hasFP16() ? ARM::FK_VFPV3_FP16 : ARM::FK_VFPV3));
-    else if (STI.hasVFP2())
-      ATS.emitFPU(ARM::FK_VFPV2);
-  }
+  // Emit build attributes for the available hardware.
+  ATS.emitTargetAttributes(STI);
 
   // RW data addressing.
   if (isPositionIndependent()) {
     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
                       ARMBuildAttrs::AddressRWPCRel);
   } else if (STI.isRWPI()) {
     // RWPI specific attributes.
     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
void ARMAsmPrinter::emitAttributes() {
   // equivalent of GCC's -ffinite-math-only flag.
   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
                       ARMBuildAttrs::Allowed);
   else
     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
                       ARMBuildAttrs::AllowIEEE754);
 
-  if (STI.allowsUnalignedMem())
-    ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
-                      ARMBuildAttrs::Allowed);
-  else
-    ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
-                      ARMBuildAttrs::Not_Allowed);
-
   // FIXME: add more flags to ARMBuildAttributes.h
   // 8-bytes alignment stuff.
   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
 
-  // ABI_HardFP_use attribute to indicate single precision FP.
-  if (STI.isFPOnlySP())
-    ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
-                      ARMBuildAttrs::HardFPSinglePrecision);
-
   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
   if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
 
-  // FIXME: Should we signal R9 usage?
-
-  if (STI.hasFP16())
-    ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
-
   // FIXME: To support emitting this build attribute as GCC does, the
   // -mfp16-format option and associated plumbing must be
   // supported. For now the __fp16 type is exposed by default, so this
   // attribute should be emitted with value 1.
   ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
                     ARMBuildAttrs::FP16FormatIEEE);
 
-  if (STI.hasMPExtension())
-    ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
-
-  // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
-  // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
-  // It is not possible to produce DisallowDIV: if hwdiv is present in the base
-  // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
-  // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
-  // otherwise, the default value (AllowDIVIfExists) applies.
-  if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
-    ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
-
-  if (STI.hasDSP() && isV8M(&STI))
-    ATS.emitAttribute(ARMBuildAttrs::DSP_extension, ARMBuildAttrs::Allowed);
-
   if (MMI) {
     if (const Module *SourceModule = MMI->getModule()) {
       // ABI_PCS_wchar_t to indicate wchar_t width
       // FIXME: There is no way to emit value 0 (wchar_t prohibited).
       if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
               SourceModule->getModuleFlag("wchar_size"))) {
         int WCharWidth = WCharWidthValue->getZExtValue();
         assert((WCharWidth == 2 || WCharWidth == 4) &&
if (STI.isRWPI())
     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
                       ARMBuildAttrs::R9IsSB);
   else if (STI.isR9Reserved())
     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
                       ARMBuildAttrs::R9Reserved);
   else
     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
                       ARMBuildAttrs::R9IsGPR);
-
-  if (STI.hasTrustZone() && STI.hasVirtualization())
-    ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
-                      ARMBuildAttrs::AllowTZVirtualization);
-  else if (STI.hasTrustZone())
-    ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
-                      ARMBuildAttrs::AllowTZ);
-  else if (STI.hasVirtualization())
-    ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
-                      ARMBuildAttrs::AllowVirtualization);
 }
 
 //===----------------------------------------------------------------------===//
 
 static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
                              unsigned LabelId, MCContext &Ctx) {
 
   MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
                           "Accept in both ISAs, emit implicit ITs in Thumb"),
                clEnumValN(ImplicitItModeTy::Never, "never",
                           "Warn in ARM, reject in Thumb"),
                clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
                           "Accept in ARM, reject in Thumb"),
                clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
                           "Warn in ARM, emit implicit ITs in Thumb")));
 
+static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
+                                        cl::init(false));
+
 class ARMOperand;
 
 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
 
 class UnwindContext {
   MCAsmParser &Parser;
 
   typedef SmallVector<SMLoc, 4> Locs;
ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
     MCAsmParserExtension::Initialize(Parser);
 
     // Cache the MCRegisterInfo.
     MRI = getContext().getRegisterInfo();
 
     // Initialize the set of available features.
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
 
+    // Add build attributes based on the selected target.
+    if (AddBuildAttributes)
+      getTargetStreamer().emitTargetAttributes(STI);
+
     // Not in an ITBlock to start with.
     ITState.CurPosition = ~0U;
 
     NextSymbolIsThumb = false;
   }
 
   // Implementation of the MCTargetAsmParser interface:
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;

lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp

 //===- ARMTargetStreamer.cpp - ARMTargetStreamer class --*- C++ -*---------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the ARMTargetStreamer class.
 //
 //===----------------------------------------------------------------------===//
 
+#include "ARMTargetMachine.h"
 #include "llvm/MC/ConstantPools.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/ARMBuildAttributes.h"
+#include "llvm/Support/TargetParser.h"
 
 using namespace llvm;
 
 //
 // ARMTargetStreamer Implemenation
 //
 
 ARMTargetStreamer::ARMTargetStreamer(MCStreamer &S)

 void ARMTargetStreamer::emitArchExtension(unsigned ArchExt) {}
 void ARMTargetStreamer::emitObjectArch(unsigned Arch) {}
 void ARMTargetStreamer::emitFPU(unsigned FPU) {}
 void ARMTargetStreamer::finishAttributeSection() {}
 void ARMTargetStreamer::emitInst(uint32_t Inst, char Suffix) {}
 void
 ARMTargetStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) {}
 void ARMTargetStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {}
+
+static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) {
+  if (STI.getCPU() == "xscale")
+    return ARMBuildAttrs::v5TEJ;
+
+  if (STI.hasFeature(ARM::HasV8Ops)) {
+    if (STI.hasFeature(ARM::FeatureRClass))
+      return ARMBuildAttrs::v8_R;
+    return ARMBuildAttrs::v8_A;
+  } else if (STI.hasFeature(ARM::HasV8MMainlineOps))
+    return ARMBuildAttrs::v8_M_Main;
+  else if (STI.hasFeature(ARM::HasV7Ops)) {
+    if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP))
+      return ARMBuildAttrs::v7E_M;
+    return ARMBuildAttrs::v7;
+  } else if (STI.hasFeature(ARM::HasV6T2Ops))
+    return ARMBuildAttrs::v6T2;
+  else if (STI.hasFeature(ARM::HasV8MBaselineOps))
+    return ARMBuildAttrs::v8_M_Base;
+  else if (STI.hasFeature(ARM::HasV6MOps))
+    return ARMBuildAttrs::v6S_M;
+  else if (STI.hasFeature(ARM::HasV6Ops))
+    return ARMBuildAttrs::v6;
+  else if (STI.hasFeature(ARM::HasV5TEOps))
+    return ARMBuildAttrs::v5TE;
+  else if (STI.hasFeature(ARM::HasV5TOps))
+    return ARMBuildAttrs::v5T;
+  else if (STI.hasFeature(ARM::HasV4TOps))
+    return ARMBuildAttrs::v4T;
+  else
+    return ARMBuildAttrs::v4;
+}
+
+static bool isV8M(const MCSubtargetInfo &STI) {
+  // Note that v8M Baseline is a subset of v6T2!
+  return (STI.hasFeature(ARM::HasV8MBaselineOps) &&
+          !STI.hasFeature(ARM::HasV6T2Ops)) ||
+         STI.hasFeature(ARM::HasV8MMainlineOps);
+}
+
+/// Emit the build attributes that only depend on the hardware that we expect
+// /to be available, and not on the ABI, or any source-language choices.
+void ARMTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
+  switchVendor("aeabi");
+
+  const StringRef CPUString = STI.getCPU();
+  if (!CPUString.empty() && !CPUString.startswith("generic")) {
+    // FIXME: remove krait check when GNU tools support krait cpu
+    if (STI.hasFeature(ARM::ProcKrait)) {
+      emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
+      // We consider krait as a "cortex-a9" + hwdiv CPU
+      // Enable hwdiv through ".arch_extension idiv"
+      if (STI.hasFeature(ARM::FeatureHWDiv) ||
+          STI.hasFeature(ARM::FeatureHWDivARM))
+        emitArchExtension(ARM::AEK_HWDIV | ARM::AEK_HWDIVARM);
+    } else {
+      emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
+    }
+  }
+
+  emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(STI));
+
+  if (STI.hasFeature(ARM::FeatureAClass)) {
+    emitAttribute(ARMBuildAttrs::CPU_arch_profile,
+                      ARMBuildAttrs::ApplicationProfile);
+  } else if (STI.hasFeature(ARM::FeatureRClass)) {
+    emitAttribute(ARMBuildAttrs::CPU_arch_profile,
+                      ARMBuildAttrs::RealTimeProfile);
+  } else if (STI.hasFeature(ARM::FeatureMClass)) {
+    emitAttribute(ARMBuildAttrs::CPU_arch_profile,
+                      ARMBuildAttrs::MicroControllerProfile);
+  }
+
+  emitAttribute(ARMBuildAttrs::ARM_ISA_use, STI.hasFeature(ARM::FeatureNoARM)
+                                                ? ARMBuildAttrs::Not_Allowed
+                                                : ARMBuildAttrs::Allowed);
+
+  if (isV8M(STI)) {
+    emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
+                      ARMBuildAttrs::AllowThumbDerived);
+  } else if (STI.hasFeature(ARM::FeatureThumb2)) {
+    emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
+                      ARMBuildAttrs::AllowThumb32);
+  } else if (STI.hasFeature(ARM::HasV4TOps)) {
+    emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
+  }
+
+  if (STI.hasFeature(ARM::FeatureNEON)) {
+    /* NEON is not exactly a VFP architecture, but GAS emit one of
+     * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
+    if (STI.hasFeature(ARM::FeatureFPARMv8)) {
+      if (STI.hasFeature(ARM::FeatureCrypto))
+        emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
+      else
+        emitFPU(ARM::FK_NEON_FP_ARMV8);
+    } else if (STI.hasFeature(ARM::FeatureVFP4))
+      emitFPU(ARM::FK_NEON_VFPV4);
+    else
+      emitFPU(STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_NEON_FP16
+                                               : ARM::FK_NEON);
+    // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
+    if (STI.hasFeature(ARM::HasV8Ops))
+      emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
+                    STI.hasFeature(ARM::HasV8_1aOps)
+                        ? ARMBuildAttrs::AllowNeonARMv8_1a
+                        : ARMBuildAttrs::AllowNeonARMv8);
+  } else {
+    if (STI.hasFeature(ARM::FeatureFPARMv8))
+      // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
+      // FPU, but there are two different names for it depending on the CPU.
+      emitFPU(STI.hasFeature(ARM::FeatureD16)
+                  ? (STI.hasFeature(ARM::FeatureVFPOnlySP) ? ARM::FK_FPV5_SP_D16
+                                                           : ARM::FK_FPV5_D16)
+                  : ARM::FK_FP_ARMV8);
+    else if (STI.hasFeature(ARM::FeatureVFP4))
+      emitFPU(STI.hasFeature(ARM::FeatureD16)
+                  ? (STI.hasFeature(ARM::FeatureVFPOnlySP) ? ARM::FK_FPV4_SP_D16
+                                                           : ARM::FK_VFPV4_D16)
+                  : ARM::FK_VFPV4);
+    else if (STI.hasFeature(ARM::FeatureVFP3))
+      emitFPU(
+          STI.hasFeature(ARM::FeatureD16)
+              // +d16
+              ? (STI.hasFeature(ARM::FeatureVFPOnlySP)
+                     ? (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16
+                                                         : ARM::FK_VFPV3XD)
+                     : (STI.hasFeature(ARM::FeatureFP16)
+                            ? ARM::FK_VFPV3_D16_FP16
+                            : ARM::FK_VFPV3_D16))
+              // -d16
+              : (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3_FP16
+                                                  : ARM::FK_VFPV3));
+    else if (STI.hasFeature(ARM::FeatureVFP2))
+      emitFPU(ARM::FK_VFPV2);
+  }
+
+  // ABI_HardFP_use attribute to indicate single precision FP.
+  if (STI.hasFeature(ARM::FeatureVFPOnlySP))
+    emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
+                  ARMBuildAttrs::HardFPSinglePrecision);
+
+  if (STI.hasFeature(ARM::FeatureFP16))
+    emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
+
+  if (STI.hasFeature(ARM::FeatureMP))
+    emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
+
+  // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
+  // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
+  // It is not possible to produce DisallowDIV: if hwdiv is present in the base
+  // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
+  // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
+  // otherwise, the default value (AllowDIVIfExists) applies.
+  if (STI.hasFeature(ARM::FeatureHWDivARM) && !STI.hasFeature(ARM::HasV8Ops))
+    emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
+
+  if (STI.hasFeature(ARM::FeatureDSP) && isV8M(STI))
+    emitAttribute(ARMBuildAttrs::DSP_extension, ARMBuildAttrs::Allowed);
+
+  if (STI.hasFeature(ARM::FeatureStrictAlign))
+    emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
+                  ARMBuildAttrs::Not_Allowed);
+  else
+    emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
+                  ARMBuildAttrs::Allowed);
+
+  if (STI.hasFeature(ARM::FeatureTrustZone) &&
+      STI.hasFeature(ARM::FeatureVirtualization))
+    emitAttribute(ARMBuildAttrs::Virtualization_use,
+                  ARMBuildAttrs::AllowTZVirtualization);
+  else if (STI.hasFeature(ARM::FeatureTrustZone))
+    emitAttribute(ARMBuildAttrs::Virtualization_use, ARMBuildAttrs::AllowTZ);
+  else if (STI.hasFeature(ARM::FeatureVirtualization))
+    emitAttribute(ARMBuildAttrs::Virtualization_use,
+                  ARMBuildAttrs::AllowVirtualization);
+}

test/CodeGen/ARM/build-attributes.ll

 ; XSCALE:      .eabi_attribute 8, 1
 ; XSCALE:      .eabi_attribute 9, 1
 
 ; DYN-ROUNDING: .eabi_attribute 19, 1
 
 ; V6:   .eabi_attribute 6, 6
 ; V6:   .eabi_attribute 8, 1
 ;; We assume round-to-nearest by default (matches GCC)
+; V6-NOT:   .eabi_attribute 27
+; V6-NOT:    .eabi_attribute 36
+; V6-NOT:    .eabi_attribute 42
+; V6-NOT:  .eabi_attribute 44
+; V6-NOT:    .eabi_attribute 68
 ; V6-NOT:   .eabi_attribute 19
 ;; The default choice made by llc is for a V6 CPU without an FPU.
 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
 ;; software floating-point support. The choice is not important for targets without
 ;; FPU support!
 ; V6:   .eabi_attribute 20, 1
 ; V6:   .eabi_attribute 21, 1
 ; V6-NOT:   .eabi_attribute 22
 ; V6:   .eabi_attribute 23, 3
 ; V6:   .eabi_attribute 24, 1
 ; V6:   .eabi_attribute 25, 1
-; V6-NOT:   .eabi_attribute 27
 ; V6-NOT:   .eabi_attribute 28
-; V6-NOT:    .eabi_attribute 36
 ; V6:    .eabi_attribute 38, 1
-; V6-NOT:    .eabi_attribute 42
-; V6-NOT:  .eabi_attribute 44
-; V6-NOT:    .eabi_attribute 68
 
 ; V6-FAST-NOT:   .eabi_attribute 19
 ;; Despite the V6 CPU having no FPU by default, we chose to flush to
 ;; positive zero here. There's no hardware support doing this, but the
 ;; fast maths software library might.
 ; V6-FAST-NOT:   .eabi_attribute 20
 ; V6-FAST-NOT:   .eabi_attribute 21
 ; V6-FAST-NOT:   .eabi_attribute 22
 ; V6-FAST:   .eabi_attribute 23, 1
 
 ;; We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for
 ;; V6-M, however we don't model the OS extension so this is fine.
 ; V6M:  .eabi_attribute 6, 12
-; V6M-NOT:  .eabi_attribute 7
+; V6M:  .eabi_attribute 7, 77
 ; V6M:  .eabi_attribute 8, 0
 ; V6M:  .eabi_attribute 9, 1
+; V6M-NOT:  .eabi_attribute 27
+; V6M-NOT:  .eabi_attribute 36
+; V6M-NOT:  .eabi_attribute 42
+; V6M-NOT:  .eabi_attribute 44
+; V6M-NOT:  .eabi_attribute 68
 ; V6M-NOT:   .eabi_attribute 19
 ;; The default choice made by llc is for a V6M CPU without an FPU.
 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
 ;; software floating-point support. The choice is not important for targets without
 ;; FPU support!
 ; V6M:  .eabi_attribute 20, 1
 ; V6M:   .eabi_attribute 21, 1
 ; V6M-NOT:   .eabi_attribute 22
 ; V6M:   .eabi_attribute 23, 3
 ; V6M:  .eabi_attribute 24, 1
 ; V6M:  .eabi_attribute 25, 1
-; V6M-NOT:  .eabi_attribute 27
 ; V6M-NOT:  .eabi_attribute 28
-; V6M-NOT:  .eabi_attribute 36
 ; V6M:  .eabi_attribute 38, 1
-; V6M-NOT:  .eabi_attribute 42
-; V6M-NOT:  .eabi_attribute 44
-; V6M-NOT:  .eabi_attribute 68
 
 ; V6M-FAST-NOT:   .eabi_attribute 19
 ;; Despite the V6M CPU having no FPU by default, we chose to flush to
 ;; positive zero here. There's no hardware support doing this, but the
 ;; fast maths software library might.
 ; V6M-FAST-NOT:  .eabi_attribute 20
 ; V6M-FAST-NOT:   .eabi_attribute 21
 ; V6M-FAST-NOT:   .eabi_attribute 22
 ; V6M-FAST:   .eabi_attribute 23, 1
 
 ; ARM1156T2F-S: .cpu arm1156t2f-s
 ; ARM1156T2F-S: .eabi_attribute 6, 8
 ; ARM1156T2F-S: .eabi_attribute 8, 1
 ; ARM1156T2F-S: .eabi_attribute 9, 2
 ; ARM1156T2F-S: .fpu vfpv2
+; ARM1156T2F-S-NOT: .eabi_attribute 27
+; ARM1156T2F-S-NOT: .eabi_attribute 36
+; ARM1156T2F-S-NOT:    .eabi_attribute 42
+; ARM1156T2F-S-NOT:    .eabi_attribute 44
+; ARM1156T2F-S-NOT:    .eabi_attribute 68
 ; ARM1156T2F-S-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; ARM1156T2F-S: .eabi_attribute 20, 1
 ; ARM1156T2F-S: .eabi_attribute 21, 1
 ; ARM1156T2F-S-NOT: .eabi_attribute 22
 ; ARM1156T2F-S: .eabi_attribute 23, 3
 ; ARM1156T2F-S: .eabi_attribute 24, 1
 ; ARM1156T2F-S: .eabi_attribute 25, 1
-; ARM1156T2F-S-NOT: .eabi_attribute 27
 ; ARM1156T2F-S-NOT: .eabi_attribute 28
-; ARM1156T2F-S-NOT: .eabi_attribute 36
 ; ARM1156T2F-S: .eabi_attribute 38, 1
-; ARM1156T2F-S-NOT:    .eabi_attribute 42
-; ARM1156T2F-S-NOT:    .eabi_attribute 44
-; ARM1156T2F-S-NOT:    .eabi_attribute 68
 
 ; ARM1156T2F-S-FAST-NOT:   .eabi_attribute 19
 ;; V6 cores default to flush to positive zero (value 0). Note that value 2 is also equally
 ;; valid for this core, it's an implementation defined question as to which of 0 and 2 you
 ;; select. LLVM historically picks 0.
 ; ARM1156T2F-S-FAST-NOT: .eabi_attribute 20
 ; ARM1156T2F-S-FAST-NOT:   .eabi_attribute 21
 ; ARM1156T2F-S-FAST-NOT:   .eabi_attribute 22
 ; ARM1156T2F-S-FAST:   .eabi_attribute 23, 1
 
 ; V7M:  .eabi_attribute 6, 10
 ; V7M:  .eabi_attribute 7, 77
 ; V7M:  .eabi_attribute 8, 0
 ; V7M:  .eabi_attribute 9, 2
+; V7M-NOT:  .eabi_attribute 27
+; V7M-NOT:  .eabi_attribute 36
+; V7M-NOT:  .eabi_attribute 42
+; V7M-NOT:  .eabi_attribute 44
+; V7M-NOT:  .eabi_attribute 68
 ; V7M-NOT:   .eabi_attribute 19
 ;; The default choice made by llc is for a V7M CPU without an FPU.
 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
 ;; software floating-point support. The choice is not important for targets without
 ;; FPU support!
 ; V7M:  .eabi_attribute 20, 1
 ; V7M: .eabi_attribute 21, 1
 ; V7M-NOT: .eabi_attribute 22
 ; V7M: .eabi_attribute 23, 3
 ; V7M:  .eabi_attribute 24, 1
 ; V7M:  .eabi_attribute 25, 1
-; V7M-NOT:  .eabi_attribute 27
 ; V7M-NOT:  .eabi_attribute 28
-; V7M-NOT:  .eabi_attribute 36
 ; V7M:  .eabi_attribute 38, 1
-; V7M-NOT:  .eabi_attribute 42
-; V7M-NOT:  .eabi_attribute 44
-; V7M-NOT:  .eabi_attribute 68
 
 ; V7M-FAST-NOT:   .eabi_attribute 19
 ;; Despite the V7M CPU having no FPU by default, we chose to flush
 ;; preserving sign. This matches what the hardware would do in the
 ;; architecture revision were to exist on the current target.
 ; V7M-FAST:  .eabi_attribute 20, 2
 ; V7M-FAST-NOT:   .eabi_attribute 21
 ; V7M-FAST-NOT:   .eabi_attribute 22
 ; V7M-FAST:   .eabi_attribute 23, 1
 
 ; V7:      .syntax unified
 ; V7: .eabi_attribute 6, 10
+; V7-NOT: .eabi_attribute 27
+; V7-NOT: .eabi_attribute 36
+; V7-NOT:    .eabi_attribute 42
+; V7-NOT:    .eabi_attribute 44
+; V7-NOT:    .eabi_attribute 68
 ; V7-NOT:   .eabi_attribute 19
 ;; In safe-maths mode we default to an IEEE 754 compliant choice.
 ; V7: .eabi_attribute 20, 1
 ; V7: .eabi_attribute 21, 1
 ; V7-NOT: .eabi_attribute 22
 ; V7: .eabi_attribute 23, 3
 ; V7: .eabi_attribute 24, 1
 ; V7: .eabi_attribute 25, 1
-; V7-NOT: .eabi_attribute 27
 ; V7-NOT: .eabi_attribute 28
-; V7-NOT: .eabi_attribute 36
 ; V7: .eabi_attribute 38, 1
-; V7-NOT:    .eabi_attribute 42
-; V7-NOT:    .eabi_attribute 44
-; V7-NOT:    .eabi_attribute 68
 
 ; V7-FAST-NOT:   .eabi_attribute 19
 ;; The default CPU does have an FPU and it must be VFPv3 or better, so it flushes
 ;; denormals to zero preserving the sign.
 ; V7-FAST: .eabi_attribute 20, 2
 ; V7-FAST-NOT:   .eabi_attribute 21
 ; V7-FAST-NOT:   .eabi_attribute 22
 ; V7-FAST:   .eabi_attribute 23, 1
 
 ; V7VE:      .syntax unified
 ; V7VE: .eabi_attribute 6, 10   @ Tag_CPU_arch
 ; V7VE: .eabi_attribute 7, 65   @ Tag_CPU_arch_profile
 ; V7VE: .eabi_attribute 8, 1    @ Tag_ARM_ISA_use
 ; V7VE: .eabi_attribute 9, 2    @ Tag_THUMB_ISA_use
+; V7VE: .eabi_attribute 42, 1   @ Tag_MPextension_use
+; V7VE: .eabi_attribute 44, 2   @ Tag_DIV_use
+; V7VE: .eabi_attribute 68, 3   @ Tag_Virtualization_use
 ; V7VE: .eabi_attribute 17, 1   @ Tag_ABI_PCS_GOT_use
 ; V7VE: .eabi_attribute 20, 1   @ Tag_ABI_FP_denormal
 ; V7VE: .eabi_attribute 21, 1   @ Tag_ABI_FP_exceptions
 ; V7VE: .eabi_attribute 23, 3   @ Tag_ABI_FP_number_model
 ; V7VE: .eabi_attribute 24, 1   @ Tag_ABI_align_needed
 ; V7VE: .eabi_attribute 25, 1   @ Tag_ABI_align_preserved
 ; V7VE: .eabi_attribute 38, 1   @ Tag_ABI_FP_16bit_format
-; V7VE: .eabi_attribute 42, 1   @ Tag_MPextension_use
-; V7VE: .eabi_attribute 44, 2   @ Tag_DIV_use
-; V7VE: .eabi_attribute 68, 3   @ Tag_Virtualization_use
 
 ; V8:      .syntax unified
 ; V8: .eabi_attribute 67, "2.09"
 ; V8: .eabi_attribute 6, 14
+; V8-NOT: .eabi_attribute 44
 ; V8-NOT:   .eabi_attribute 19
 ; V8: .eabi_attribute 20, 1
 ; V8: .eabi_attribute 21, 1
 ; V8-NOT: .eabi_attribute 22
 ; V8: .eabi_attribute 23, 3
-; V8-NOT: .eabi_attribute 44
 
 ; V8-FAST-NOT:   .eabi_attribute 19
 ;; The default does have an FPU, and for V8-A, it flushes preserving sign.
 ; V8-FAST: .eabi_attribute 20, 2
 ; V8-FAST-NOT: .eabi_attribute 21
 ; V8-FAST-NOT: .eabi_attribute 22
 ; V8-FAST: .eabi_attribute 23, 1
 

 ; CORTEX-A7-NOFPU: .eabi_attribute      9, 2
 ; CORTEX-A7-FPUV4: .eabi_attribute      9, 2
 
 ; CORTEX-A7-CHECK: .fpu neon-vfpv4
 ; CORTEX-A7-NOFPU-NOT: .fpu
 ; CORTEX-A7-FPUV4: .fpu vfpv4
 
 ; CORTEX-A7-CHECK-NOT:   .eabi_attribute 19
+
+; Tag_FP_HP_extension
+; CORTEX-A7-CHECK: .eabi_attribute      36, 1
+; CORTEX-A7-NOFPU-NOT: .eabi_attribute  36
+; CORTEX-A7-FPUV4: .eabi_attribute      36, 1
+
+; Tag_MPextension_use
+; CORTEX-A7-CHECK: .eabi_attribute      42, 1
+; CORTEX-A7-NOFPU: .eabi_attribute      42, 1
+; CORTEX-A7-FPUV4: .eabi_attribute      42, 1
+
+; Tag_DIV_use
+; CORTEX-A7-CHECK: .eabi_attribute      44, 2
+; CORTEX-A7-NOFPU: .eabi_attribute      44, 2
+; CORTEX-A7-FPUV4: .eabi_attribute      44, 2
+
+; Tag_DSP_extension
+; CORTEX-A7-CHECK-NOT: .eabi_attribute      46
+
+; Tag_Virtualization_use
+; CORTEX-A7-CHECK: .eabi_attribute      68, 3
+; CORTEX-A7-NOFPU: .eabi_attribute      68, 3
+; CORTEX-A7-FPUV4: .eabi_attribute      68, 3
+
 ; Tag_ABI_FP_denormal
 ;; We default to IEEE 754 compliance
 ; CORTEX-A7-CHECK: .eabi_attribute      20, 1
 ;; The A7 has VFPv3 support by default, so flush preserving sign.
 ; CORTEX-A7-CHECK-FAST: .eabi_attribute 20, 2
 ; CORTEX-A7-NOFPU: .eabi_attribute      20, 1
 ;; Despite there being no FPU, we chose to flush to zero preserving
 ;; sign. This matches what the hardware would do for this architecture

 ; CORTEX-A7-NOFPU: .eabi_attribute      24, 1
 ; CORTEX-A7-FPUV4: .eabi_attribute      24, 1
 
 ; Tag_ABI_align_preserved
 ; CORTEX-A7-CHECK: .eabi_attribute      25, 1
 ; CORTEX-A7-NOFPU: .eabi_attribute      25, 1
 ; CORTEX-A7-FPUV4: .eabi_attribute      25, 1
 
-; Tag_FP_HP_extension
-; CORTEX-A7-CHECK: .eabi_attribute      36, 1
-; CORTEX-A7-NOFPU-NOT: .eabi_attribute  36
-; CORTEX-A7-FPUV4: .eabi_attribute      36, 1
-
 ; Tag_FP_16bit_format
 ; CORTEX-A7-CHECK: .eabi_attribute      38, 1
 ; CORTEX-A7-NOFPU: .eabi_attribute      38, 1
 ; CORTEX-A7-FPUV4: .eabi_attribute      38, 1
 
-; Tag_MPextension_use
-; CORTEX-A7-CHECK: .eabi_attribute      42, 1
-; CORTEX-A7-NOFPU: .eabi_attribute      42, 1
-; CORTEX-A7-FPUV4: .eabi_attribute      42, 1
-
-; Tag_DIV_use
-; CORTEX-A7-CHECK: .eabi_attribute      44, 2
-; CORTEX-A7-NOFPU: .eabi_attribute      44, 2
-; CORTEX-A7-FPUV4: .eabi_attribute      44, 2
-
-; Tag_DSP_extension
-; CORTEX-A7-CHECK-NOT: .eabi_attribute      46
-
-; Tag_Virtualization_use
-; CORTEX-A7-CHECK: .eabi_attribute      68, 3
-; CORTEX-A7-NOFPU: .eabi_attribute      68, 3
-; CORTEX-A7-FPUV4: .eabi_attribute      68, 3
-
 ; CORTEX-A5-DEFAULT:        .cpu    cortex-a5
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 6, 10
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 7, 65
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 8, 1
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 9, 2
 ; CORTEX-A5-DEFAULT:        .fpu    neon-vfpv4
+; CORTEX-A5-DEFAULT:        .eabi_attribute 42, 1
+; CORTEX-A5-DEFAULT-NOT:        .eabi_attribute 44
+; CORTEX-A5-DEFAULT:        .eabi_attribute 68, 1
 ; CORTEX-A5-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 20, 1
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 21, 1
 ; CORTEX-A5-DEFAULT-NOT:        .eabi_attribute 22
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 23, 3
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 24, 1
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 25, 1
-; CORTEX-A5-DEFAULT:        .eabi_attribute 42, 1
-; CORTEX-A5-DEFAULT-NOT:        .eabi_attribute 44
-; CORTEX-A5-DEFAULT:        .eabi_attribute 68, 1
 
 ; CORTEX-A5-DEFAULT-FAST-NOT:   .eabi_attribute 19
 ;; The A5 defaults to a VFPv4 FPU, so it flushed preserving the sign when -ffast-math
 ;; is given.
 ; CORTEX-A5-DEFAULT-FAST:        .eabi_attribute 20, 2
 ; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 21
 ; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 22
 ; CORTEX-A5-DEFAULT-FAST: .eabi_attribute 23, 1
 
 ; CORTEX-A5-NONEON:        .cpu    cortex-a5
 ; CORTEX-A5-NONEON:        .eabi_attribute 6, 10
 ; CORTEX-A5-NONEON:        .eabi_attribute 7, 65
 ; CORTEX-A5-NONEON:        .eabi_attribute 8, 1
 ; CORTEX-A5-NONEON:        .eabi_attribute 9, 2
 ; CORTEX-A5-NONEON:        .fpu    vfpv4-d16
+; CORTEX-A5-NONEON:        .eabi_attribute 42, 1
+; CORTEX-A5-NONEON:        .eabi_attribute 68, 1
 ;; We default to IEEE 754 compliance
 ; CORTEX-A5-NONEON:        .eabi_attribute 20, 1
 ; CORTEX-A5-NONEON:        .eabi_attribute 21, 1
 ; CORTEX-A5-NONEON-NOT:    .eabi_attribute 22
 ; CORTEX-A5-NONEON:        .eabi_attribute 23, 3
 ; CORTEX-A5-NONEON:        .eabi_attribute 24, 1
 ; CORTEX-A5-NONEON:        .eabi_attribute 25, 1
-; CORTEX-A5-NONEON:        .eabi_attribute 42, 1
-; CORTEX-A5-NONEON:        .eabi_attribute 68, 1
 
 ; CORTEX-A5-NONEON-FAST-NOT:   .eabi_attribute 19
 ;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math
 ;; is given.
 ; CORTEX-A5-NONEON-FAST:        .eabi_attribute 20, 2
 ; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 21
 ; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 22
 ; CORTEX-A5-NONEON-FAST: .eabi_attribute 23, 1
 
 ; CORTEX-A5-NOFPU:        .cpu    cortex-a5
 ; CORTEX-A5-NOFPU:        .eabi_attribute 6, 10
 ; CORTEX-A5-NOFPU:        .eabi_attribute 7, 65
 ; CORTEX-A5-NOFPU:        .eabi_attribute 8, 1
 ; CORTEX-A5-NOFPU:        .eabi_attribute 9, 2
 ; CORTEX-A5-NOFPU-NOT:    .fpu
+; CORTEX-A5-NOFPU:        .eabi_attribute 42, 1
+; CORTEX-A5-NOFPU:        .eabi_attribute 68, 1
 ; CORTEX-A5-NOFPU-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A5-NOFPU:        .eabi_attribute 20, 1
 ; CORTEX-A5-NOFPU:        .eabi_attribute 21, 1
 ; CORTEX-A5-NOFPU-NOT:    .eabi_attribute 22
 ; CORTEX-A5-NOFPU:        .eabi_attribute 23, 3
 ; CORTEX-A5-NOFPU:        .eabi_attribute 24, 1
 ; CORTEX-A5-NOFPU:        .eabi_attribute 25, 1
-; CORTEX-A5-NOFPU:        .eabi_attribute 42, 1
-; CORTEX-A5-NOFPU:        .eabi_attribute 68, 1
 
 ; CORTEX-A5-NOFPU-FAST-NOT:   .eabi_attribute 19
 ;; Despite there being no FPU, we chose to flush to zero preserving
 ;; sign. This matches what the hardware would do for this architecture
 ;; revision.
 ; CORTEX-A5-NOFPU-FAST: .eabi_attribute 20, 2
 ; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 21
 ; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 22
 ; CORTEX-A5-NOFPU-FAST: .eabi_attribute 23, 1
 
 ; CORTEX-A8-SOFT:  .cpu cortex-a8
 ; CORTEX-A8-SOFT:  .eabi_attribute 6, 10
 ; CORTEX-A8-SOFT:  .eabi_attribute 7, 65
 ; CORTEX-A8-SOFT:  .eabi_attribute 8, 1
 ; CORTEX-A8-SOFT:  .eabi_attribute 9, 2
 ; CORTEX-A8-SOFT:  .fpu neon
+; CORTEX-A8-SOFT-NOT:  .eabi_attribute 27
+; CORTEX-A8-SOFT-NOT:  .eabi_attribute 36, 1
+; CORTEX-A8-SOFT-NOT:  .eabi_attribute 42, 1
+; CORTEX-A8-SOFT-NOT:  .eabi_attribute 44
+; CORTEX-A8-SOFT:  .eabi_attribute 68, 1
 ; CORTEX-A8-SOFT-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A8-SOFT:  .eabi_attribute 20, 1
 ; CORTEX-A8-SOFT:  .eabi_attribute 21, 1
 ; CORTEX-A8-SOFT-NOT:  .eabi_attribute 22
 ; CORTEX-A8-SOFT:  .eabi_attribute 23, 3
 ; CORTEX-A8-SOFT:  .eabi_attribute 24, 1
 ; CORTEX-A8-SOFT:  .eabi_attribute 25, 1
-; CORTEX-A8-SOFT-NOT:  .eabi_attribute 27
 ; CORTEX-A8-SOFT-NOT:  .eabi_attribute 28
-; CORTEX-A8-SOFT-NOT:  .eabi_attribute 36, 1
 ; CORTEX-A8-SOFT:  .eabi_attribute 38, 1
-; CORTEX-A8-SOFT-NOT:  .eabi_attribute 42, 1
-; CORTEX-A8-SOFT-NOT:  .eabi_attribute 44
-; CORTEX-A8-SOFT:  .eabi_attribute 68, 1
 
 ; CORTEX-A9-SOFT:  .cpu cortex-a9
 ; CORTEX-A9-SOFT:  .eabi_attribute 6, 10
 ; CORTEX-A9-SOFT:  .eabi_attribute 7, 65
 ; CORTEX-A9-SOFT:  .eabi_attribute 8, 1
 ; CORTEX-A9-SOFT:  .eabi_attribute 9, 2
 ; CORTEX-A9-SOFT:  .fpu neon
+; CORTEX-A9-SOFT-NOT:  .eabi_attribute 27
+; CORTEX-A9-SOFT:  .eabi_attribute 36, 1
+; CORTEX-A9-SOFT:  .eabi_attribute 42, 1
+; CORTEX-A9-SOFT-NOT:  .eabi_attribute 44
+; CORTEX-A9-SOFT:  .eabi_attribute 68, 1
 ; CORTEX-A9-SOFT-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A9-SOFT:  .eabi_attribute 20, 1
 ; CORTEX-A9-SOFT:  .eabi_attribute 21, 1
 ; CORTEX-A9-SOFT-NOT:  .eabi_attribute 22
 ; CORTEX-A9-SOFT:  .eabi_attribute 23, 3
 ; CORTEX-A9-SOFT:  .eabi_attribute 24, 1
 ; CORTEX-A9-SOFT:  .eabi_attribute 25, 1
-; CORTEX-A9-SOFT-NOT:  .eabi_attribute 27
 ; CORTEX-A9-SOFT-NOT:  .eabi_attribute 28
-; CORTEX-A9-SOFT:  .eabi_attribute 36, 1
 ; CORTEX-A9-SOFT:  .eabi_attribute 38, 1
-; CORTEX-A9-SOFT:  .eabi_attribute 42, 1
-; CORTEX-A9-SOFT-NOT:  .eabi_attribute 44
-; CORTEX-A9-SOFT:  .eabi_attribute 68, 1
 
 ; CORTEX-A8-SOFT-FAST-NOT:   .eabi_attribute 19
 ; CORTEX-A9-SOFT-FAST-NOT:   .eabi_attribute 19
 ;; The A9 defaults to a VFPv3 FPU, so it flushes preserving the sign when
 ;; -ffast-math is specified.
 ; CORTEX-A8-SOFT-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A9-SOFT-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 21
 ; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 22
 ; CORTEX-A5-SOFT-FAST: .eabi_attribute 23, 1
 
 ; CORTEX-A8-HARD:  .cpu cortex-a8
 ; CORTEX-A8-HARD:  .eabi_attribute 6, 10
 ; CORTEX-A8-HARD:  .eabi_attribute 7, 65
 ; CORTEX-A8-HARD:  .eabi_attribute 8, 1
 ; CORTEX-A8-HARD:  .eabi_attribute 9, 2
 ; CORTEX-A8-HARD:  .fpu neon
+; CORTEX-A8-HARD-NOT:  .eabi_attribute 27
+; CORTEX-A8-HARD-NOT:  .eabi_attribute 36, 1
+; CORTEX-A8-HARD-NOT:  .eabi_attribute 42, 1
+; CORTEX-A8-HARD:  .eabi_attribute 68, 1
 ; CORTEX-A8-HARD-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A8-HARD:  .eabi_attribute 20, 1
 ; CORTEX-A8-HARD:  .eabi_attribute 21, 1
 ; CORTEX-A8-HARD-NOT:  .eabi_attribute 22
 ; CORTEX-A8-HARD:  .eabi_attribute 23, 3
 ; CORTEX-A8-HARD:  .eabi_attribute 24, 1
 ; CORTEX-A8-HARD:  .eabi_attribute 25, 1
-; CORTEX-A8-HARD-NOT:  .eabi_attribute 27
 ; CORTEX-A8-HARD:  .eabi_attribute 28, 1
-; CORTEX-A8-HARD-NOT:  .eabi_attribute 36, 1
 ; CORTEX-A8-HARD:  .eabi_attribute 38, 1
-; CORTEX-A8-HARD-NOT:  .eabi_attribute 42, 1
-; CORTEX-A8-HARD:  .eabi_attribute 68, 1
 
 
 
 ; CORTEX-A9-HARD:  .cpu cortex-a9
 ; CORTEX-A9-HARD:  .eabi_attribute 6, 10
 ; CORTEX-A9-HARD:  .eabi_attribute 7, 65
 ; CORTEX-A9-HARD:  .eabi_attribute 8, 1
 ; CORTEX-A9-HARD:  .eabi_attribute 9, 2
 ; CORTEX-A9-HARD:  .fpu neon
+; CORTEX-A9-HARD-NOT:  .eabi_attribute 27
+; CORTEX-A9-HARD:  .eabi_attribute 36, 1
+; CORTEX-A9-HARD:  .eabi_attribute 42, 1
+; CORTEX-A9-HARD:  .eabi_attribute 68, 1
 ; CORTEX-A9-HARD-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A9-HARD:  .eabi_attribute 20, 1
 ; CORTEX-A9-HARD:  .eabi_attribute 21, 1
 ; CORTEX-A9-HARD-NOT:  .eabi_attribute 22
 ; CORTEX-A9-HARD:  .eabi_attribute 23, 3
 ; CORTEX-A9-HARD:  .eabi_attribute 24, 1
 ; CORTEX-A9-HARD:  .eabi_attribute 25, 1
-; CORTEX-A9-HARD-NOT:  .eabi_attribute 27
 ; CORTEX-A9-HARD:  .eabi_attribute 28, 1
-; CORTEX-A9-HARD:  .eabi_attribute 36, 1
 ; CORTEX-A9-HARD:  .eabi_attribute 38, 1
-; CORTEX-A9-HARD:  .eabi_attribute 42, 1
-; CORTEX-A9-HARD:  .eabi_attribute 68, 1
 
 ; CORTEX-A8-HARD-FAST-NOT:   .eabi_attribute 19
 ;; The A8 defaults to a VFPv3 FPU, so it flushes preserving the sign when
 ;; -ffast-math is specified.
 ; CORTEX-A8-HARD-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A8-HARD-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-A8-HARD-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A8-HARD-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-A9-HARD-FAST-NOT:   .eabi_attribute 19
 ;; The A9 defaults to a VFPv3 FPU, so it flushes preserving the sign when
 ;; -ffast-math is specified.
 ; CORTEX-A9-HARD-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A9-HARD-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-A9-HARD-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A9-HARD-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-A12-DEFAULT:  .cpu cortex-a12
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 6, 10
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 7, 65
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 8, 1
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 9, 2
 ; CORTEX-A12-DEFAULT:  .fpu neon-vfpv4
+; CORTEX-A12-DEFAULT:  .eabi_attribute 42, 1
+; CORTEX-A12-DEFAULT:  .eabi_attribute 44, 2
+; CORTEX-A12-DEFAULT:  .eabi_attribute 68, 3
 ; CORTEX-A12-DEFAULT-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 20, 1
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 21, 1
 ; CORTEX-A12-DEFAULT-NOT:  .eabi_attribute 22
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 23, 3
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 24, 1
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 25, 1
-; CORTEX-A12-DEFAULT:  .eabi_attribute 42, 1
-; CORTEX-A12-DEFAULT:  .eabi_attribute 44, 2
-; CORTEX-A12-DEFAULT:  .eabi_attribute 68, 3
 
 ; CORTEX-A12-DEFAULT-FAST-NOT:   .eabi_attribute 19
 ;; The A12 defaults to a VFPv3 FPU, so it flushes preserving the sign when
 ;; -ffast-math is specified.
 ; CORTEX-A12-DEFAULT-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A12-HARD-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-A12-HARD-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A12-HARD-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-A12-NOFPU:  .cpu cortex-a12
 ; CORTEX-A12-NOFPU:  .eabi_attribute 6, 10
 ; CORTEX-A12-NOFPU:  .eabi_attribute 7, 65
 ; CORTEX-A12-NOFPU:  .eabi_attribute 8, 1
 ; CORTEX-A12-NOFPU:  .eabi_attribute 9, 2
 ; CORTEX-A12-NOFPU-NOT:  .fpu
+; CORTEX-A12-NOFPU:  .eabi_attribute 42, 1
+; CORTEX-A12-NOFPU:  .eabi_attribute 44, 2
+; CORTEX-A12-NOFPU:  .eabi_attribute 68, 3
 ; CORTEX-A12-NOFPU-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A12-NOFPU:  .eabi_attribute 20, 1
 ; CORTEX-A12-NOFPU:  .eabi_attribute 21, 1
 ; CORTEX-A12-NOFPU-NOT:  .eabi_attribute 22
 ; CORTEX-A12-NOFPU:  .eabi_attribute 23, 3
 ; CORTEX-A12-NOFPU:  .eabi_attribute 24, 1
 ; CORTEX-A12-NOFPU:  .eabi_attribute 25, 1
-; CORTEX-A12-NOFPU:  .eabi_attribute 42, 1
-; CORTEX-A12-NOFPU:  .eabi_attribute 44, 2
-; CORTEX-A12-NOFPU:  .eabi_attribute 68, 3
 
 ; CORTEX-A12-NOFPU-FAST-NOT:   .eabi_attribute 19
 ;; Despite there being no FPU, we chose to flush to zero preserving
 ;; sign. This matches what the hardware would do for this architecture
 ;; revision.
 ; CORTEX-A12-NOFPU-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A12-NOFPU-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-A12-NOFPU-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A12-NOFPU-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-A15: .cpu cortex-a15
 ; CORTEX-A15: .eabi_attribute 6, 10
 ; CORTEX-A15: .eabi_attribute 7, 65
 ; CORTEX-A15: .eabi_attribute 8, 1
 ; CORTEX-A15: .eabi_attribute 9, 2
 ; CORTEX-A15: .fpu neon-vfpv4
+; CORTEX-A15-NOT: .eabi_attribute 27
+; CORTEX-A15: .eabi_attribute 36, 1
+; CORTEX-A15: .eabi_attribute 42, 1
+; CORTEX-A15: .eabi_attribute 44, 2
+; CORTEX-A15: .eabi_attribute 68, 3
 ; CORTEX-A15-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A15: .eabi_attribute 20, 1
 ; CORTEX-A15: .eabi_attribute 21, 1
 ; CORTEX-A15-NOT: .eabi_attribute 22
 ; CORTEX-A15: .eabi_attribute 23, 3
 ; CORTEX-A15: .eabi_attribute 24, 1
 ; CORTEX-A15: .eabi_attribute 25, 1
-; CORTEX-A15-NOT: .eabi_attribute 27
 ; CORTEX-A15-NOT: .eabi_attribute 28
-; CORTEX-A15: .eabi_attribute 36, 1
 ; CORTEX-A15: .eabi_attribute 38, 1
-; CORTEX-A15: .eabi_attribute 42, 1
-; CORTEX-A15: .eabi_attribute 44, 2
-; CORTEX-A15: .eabi_attribute 68, 3
 
 ; CORTEX-A15-FAST-NOT:   .eabi_attribute 19
 ;; The A15 defaults to a VFPv3 FPU, so it flushes preserving the sign when
 ;; -ffast-math is specified.
 ; CORTEX-A15-FAST: .eabi_attribute 20, 2
 ; CORTEX-A15-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-A15-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A15-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-A17-DEFAULT:  .cpu cortex-a17
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 6, 10
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 7, 65
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 8, 1
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 9, 2
 ; CORTEX-A17-DEFAULT:  .fpu neon-vfpv4
+; CORTEX-A17-DEFAULT:  .eabi_attribute 42, 1
+; CORTEX-A17-DEFAULT:  .eabi_attribute 44, 2
+; CORTEX-A17-DEFAULT:  .eabi_attribute 68, 3
 ; CORTEX-A17-DEFAULT-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 20, 1
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 21, 1
 ; CORTEX-A17-DEFAULT-NOT:  .eabi_attribute 22
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 23, 3
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 24, 1
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 25, 1
-; CORTEX-A17-DEFAULT:  .eabi_attribute 42, 1
-; CORTEX-A17-DEFAULT:  .eabi_attribute 44, 2
-; CORTEX-A17-DEFAULT:  .eabi_attribute 68, 3
 
 ; CORTEX-A17-FAST-NOT:   .eabi_attribute 19
 ;; The A17 defaults to a VFPv3 FPU, so it flushes preserving the sign when
 ;; -ffast-math is specified.
 ; CORTEX-A17-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A17-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-A17-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A17-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-A17-NOFPU:  .cpu cortex-a17
 ; CORTEX-A17-NOFPU:  .eabi_attribute 6, 10
 ; CORTEX-A17-NOFPU:  .eabi_attribute 7, 65
 ; CORTEX-A17-NOFPU:  .eabi_attribute 8, 1
 ; CORTEX-A17-NOFPU:  .eabi_attribute 9, 2
 ; CORTEX-A17-NOFPU-NOT:  .fpu
+; CORTEX-A17-NOFPU:  .eabi_attribute 42, 1
+; CORTEX-A17-NOFPU:  .eabi_attribute 44, 2
+; CORTEX-A17-NOFPU:  .eabi_attribute 68, 3
 ; CORTEX-A17-NOFPU-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A17-NOFPU:  .eabi_attribute 20, 1
 ; CORTEX-A17-NOFPU:  .eabi_attribute 21, 1
 ; CORTEX-A17-NOFPU-NOT:  .eabi_attribute 22
 ; CORTEX-A17-NOFPU:  .eabi_attribute 23, 3
 ; CORTEX-A17-NOFPU:  .eabi_attribute 24, 1
 ; CORTEX-A17-NOFPU:  .eabi_attribute 25, 1
-; CORTEX-A17-NOFPU:  .eabi_attribute 42, 1
-; CORTEX-A17-NOFPU:  .eabi_attribute 44, 2
-; CORTEX-A17-NOFPU:  .eabi_attribute 68, 3
 
 ; CORTEX-A17-NOFPU-NOT:   .eabi_attribute 19
 ;; Despite there being no FPU, we chose to flush to zero preserving
 ;; sign. This matches what the hardware would do for this architecture
 ;; revision.
 ; CORTEX-A17-NOFPU-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A17-NOFPU-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-A17-NOFPU-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A17-NOFPU-FAST:  .eabi_attribute 23, 1
 
 ; Test flags -enable-no-trapping-fp-math and -denormal-fp-math:
 ; NO-TRAPPING-MATH:  .eabi_attribute 21, 0
 ; DENORMAL-IEEE:  .eabi_attribute 20, 1
 ; DENORMAL-PRESERVE-SIGN:  .eabi_attribute 20, 2
 ; DENORMAL-POSITIVE-ZERO:  .eabi_attribute 20, 0
 
 ; CORTEX-M0:  .cpu cortex-m0
 ; CORTEX-M0:  .eabi_attribute 6, 12
-; CORTEX-M0-NOT:  .eabi_attribute 7
+; CORTEX-M0:  .eabi_attribute 7, 77
 ; CORTEX-M0:  .eabi_attribute 8, 0
 ; CORTEX-M0:  .eabi_attribute 9, 1
+; CORTEX-M0-NOT:  .eabi_attribute 27
+; CORTEX-M0-NOT:  .eabi_attribute 36
+; CORTEX-M0: .eabi_attribute 34, 0
+; CORTEX-M0-NOT:  .eabi_attribute 42
+; CORTEX-M0-NOT:  .eabi_attribute 44
+; CORTEX-M0-NOT:  .eabi_attribute 68
 ; CORTEX-M0-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M0:  .eabi_attribute 20, 1
 ; CORTEX-M0:  .eabi_attribute 21, 1
 ; CORTEX-M0-NOT:  .eabi_attribute 22
 ; CORTEX-M0:  .eabi_attribute 23, 3
-; CORTEX-M0: .eabi_attribute 34, 0
 ; CORTEX-M0:  .eabi_attribute 24, 1
 ; CORTEX-M0:  .eabi_attribute 25, 1
-; CORTEX-M0-NOT:  .eabi_attribute 27
 ; CORTEX-M0-NOT:  .eabi_attribute 28
-; CORTEX-M0-NOT:  .eabi_attribute 36
 ; CORTEX-M0:  .eabi_attribute 38, 1
-; CORTEX-M0-NOT:  .eabi_attribute 42
-; CORTEX-M0-NOT:  .eabi_attribute 44
-; CORTEX-M0-NOT:  .eabi_attribute 68
 
 ; CORTEX-M0-FAST-NOT:   .eabi_attribute 19
 ;; Despite the M0 CPU having no FPU in this scenario, we chose to
 ;; flush to positive zero here. There's no hardware support doing
 ;; this, but the fast maths software library might and such behaviour
 ;; would match hardware support on this architecture revision if it
 ;; existed.
 ; CORTEX-M0-FAST-NOT:  .eabi_attribute 20
 ; CORTEX-M0-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-M0-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-M0-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-M0PLUS:  .cpu cortex-m0plus
 ; CORTEX-M0PLUS:  .eabi_attribute 6, 12
-; CORTEX-M0PLUS-NOT:  .eabi_attribute 7
+; CORTEX-M0PLUS:  .eabi_attribute 7, 77
 ; CORTEX-M0PLUS:  .eabi_attribute 8, 0
 ; CORTEX-M0PLUS:  .eabi_attribute 9, 1
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 27
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 36
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 42
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 44
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 68
 ; CORTEX-M0PLUS-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M0PLUS:  .eabi_attribute 20, 1
 ; CORTEX-M0PLUS:  .eabi_attribute 21, 1
 ; CORTEX-M0PLUS-NOT:  .eabi_attribute 22
 ; CORTEX-M0PLUS:  .eabi_attribute 23, 3
 ; CORTEX-M0PLUS:  .eabi_attribute 24, 1
 ; CORTEX-M0PLUS:  .eabi_attribute 25, 1
-; CORTEX-M0PLUS-NOT:  .eabi_attribute 27
 ; CORTEX-M0PLUS-NOT:  .eabi_attribute 28
-; CORTEX-M0PLUS-NOT:  .eabi_attribute 36
 ; CORTEX-M0PLUS:  .eabi_attribute 38, 1
-; CORTEX-M0PLUS-NOT:  .eabi_attribute 42
-; CORTEX-M0PLUS-NOT:  .eabi_attribute 44
-; CORTEX-M0PLUS-NOT:  .eabi_attribute 68
 
 ; CORTEX-M0PLUS-FAST-NOT:   .eabi_attribute 19
 ;; Despite the M0+ CPU having no FPU in this scenario, we chose to
 ;; flush to positive zero here. There's no hardware support doing
 ;; this, but the fast maths software library might and such behaviour
 ;; would match hardware support on this architecture revision if it
 ;; existed.
 ; CORTEX-M0PLUS-FAST-NOT:  .eabi_attribute 20
 ; CORTEX-M0PLUS-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-M0PLUS-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-M0PLUS-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-M1:  .cpu cortex-m1
 ; CORTEX-M1:  .eabi_attribute 6, 12
-; CORTEX-M1-NOT:  .eabi_attribute 7
+; CORTEX-M1:  .eabi_attribute 7, 77
 ; CORTEX-M1:  .eabi_attribute 8, 0
 ; CORTEX-M1:  .eabi_attribute 9, 1
+; CORTEX-M1-NOT:  .eabi_attribute 27
+; CORTEX-M1-NOT:  .eabi_attribute 36
+; CORTEX-M1-NOT:  .eabi_attribute 42
+; CORTEX-M1-NOT:  .eabi_attribute 44
+; CORTEX-M1-NOT:  .eabi_attribute 68
 ; CORTEX-M1-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M1:  .eabi_attribute 20, 1
 ; CORTEX-M1:  .eabi_attribute 21, 1
 ; CORTEX-M1-NOT:  .eabi_attribute 22
 ; CORTEX-M1:  .eabi_attribute 23, 3
 ; CORTEX-M1:  .eabi_attribute 24, 1
 ; CORTEX-M1:  .eabi_attribute 25, 1
-; CORTEX-M1-NOT:  .eabi_attribute 27
 ; CORTEX-M1-NOT:  .eabi_attribute 28
-; CORTEX-M1-NOT:  .eabi_attribute 36
 ; CORTEX-M1:  .eabi_attribute 38, 1
-; CORTEX-M1-NOT:  .eabi_attribute 42
-; CORTEX-M1-NOT:  .eabi_attribute 44
-; CORTEX-M1-NOT:  .eabi_attribute 68
 
 ; CORTEX-M1-FAST-NOT:   .eabi_attribute 19
 ;; Despite the M1 CPU having no FPU in this scenario, we chose to
 ;; flush to positive zero here. There's no hardware support doing
 ;; this, but the fast maths software library might and such behaviour
 ;; would match hardware support on this architecture revision if it
 ;; existed.
 ; CORTEX-M1-FAST-NOT:  .eabi_attribute 20
 ; CORTEX-M1-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-M1-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-M1-FAST:  .eabi_attribute 23, 1
 
 ; SC000:  .cpu sc000
 ; SC000:  .eabi_attribute 6, 12
-; SC000-NOT:  .eabi_attribute 7
+; SC000:  .eabi_attribute 7, 77
 ; SC000:  .eabi_attribute 8, 0
 ; SC000:  .eabi_attribute 9, 1
+; SC000-NOT:  .eabi_attribute 27
+; SC000-NOT:  .eabi_attribute 42
+; SC000-NOT:  .eabi_attribute 44
+; SC000-NOT:  .eabi_attribute 68
 ; SC000-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; SC000:  .eabi_attribute 20, 1
 ; SC000:  .eabi_attribute 21, 1
 ; SC000-NOT:  .eabi_attribute 22
 ; SC000:  .eabi_attribute 23, 3
 ; SC000:  .eabi_attribute 24, 1
 ; SC000:  .eabi_attribute 25, 1
-; SC000-NOT:  .eabi_attribute 27
 ; SC000-NOT:  .eabi_attribute 28
-; SC000-NOT:  .eabi_attribute 36
 ; SC000:  .eabi_attribute 38, 1
-; SC000-NOT:  .eabi_attribute 42
-; SC000-NOT:  .eabi_attribute 44
-; SC000-NOT:  .eabi_attribute 68
 
 ; SC000-FAST-NOT:   .eabi_attribute 19
 ;; Despite the SC000 CPU having no FPU in this scenario, we chose to
 ;; flush to positive zero here. There's no hardware support doing
 ;; this, but the fast maths software library might and such behaviour
 ;; would match hardware support on this architecture revision if it
 ;; existed.
 ; SC000-FAST-NOT:  .eabi_attribute 20
 ; SC000-FAST-NOT:  .eabi_attribute 21
 ; SC000-FAST-NOT:  .eabi_attribute 22
 ; SC000-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-M3:  .cpu cortex-m3
 ; CORTEX-M3:  .eabi_attribute 6, 10
 ; CORTEX-M3:  .eabi_attribute 7, 77
 ; CORTEX-M3:  .eabi_attribute 8, 0
 ; CORTEX-M3:  .eabi_attribute 9, 2
+; CORTEX-M3-NOT:  .eabi_attribute 27
+; CORTEX-M3-NOT:  .eabi_attribute 36
+; CORTEX-M3-NOT:  .eabi_attribute 42
+; CORTEX-M3-NOT:  .eabi_attribute 44
+; CORTEX-M3-NOT:  .eabi_attribute 68
 ; CORTEX-M3-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M3:  .eabi_attribute 20, 1
 ; CORTEX-M3:  .eabi_attribute 21, 1
 ; CORTEX-M3-NOT:  .eabi_attribute 22
 ; CORTEX-M3:  .eabi_attribute 23, 3
 ; CORTEX-M3:  .eabi_attribute 24, 1
 ; CORTEX-M3:  .eabi_attribute 25, 1
-; CORTEX-M3-NOT:  .eabi_attribute 27
 ; CORTEX-M3-NOT:  .eabi_attribute 28
-; CORTEX-M3-NOT:  .eabi_attribute 36
 ; CORTEX-M3:  .eabi_attribute 38, 1
-; CORTEX-M3-NOT:  .eabi_attribute 42
-; CORTEX-M3-NOT:  .eabi_attribute 44
-; CORTEX-M3-NOT:  .eabi_attribute 68
 
 ; CORTEX-M3-FAST-NOT:   .eabi_attribute 19
 ;; Despite there being no FPU, we chose to flush to zero preserving
 ;; sign. This matches what the hardware would do for this architecture
 ;; revision.
 ; CORTEX-M3-FAST:  .eabi_attribute 20, 2
 ; CORTEX-M3-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-M3-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-M3-FAST:  .eabi_attribute 23, 1
 
 ; SC300:  .cpu sc300
 ; SC300:  .eabi_attribute 6, 10
 ; SC300:  .eabi_attribute 7, 77
 ; SC300:  .eabi_attribute 8, 0
 ; SC300:  .eabi_attribute 9, 2
+; SC300-NOT:  .eabi_attribute 27
+; SC300-NOT:  .eabi_attribute 36
+; SC300-NOT:  .eabi_attribute 42
+; SC300-NOT:  .eabi_attribute 44
+; SC300-NOT:  .eabi_attribute 68
 ; SC300-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; SC300:  .eabi_attribute 20, 1
 ; SC300:  .eabi_attribute 21, 1
 ; SC300-NOT:  .eabi_attribute 22
 ; SC300:  .eabi_attribute 23, 3
 ; SC300:  .eabi_attribute 24, 1
 ; SC300:  .eabi_attribute 25, 1
-; SC300-NOT:  .eabi_attribute 27
 ; SC300-NOT:  .eabi_attribute 28
-; SC300-NOT:  .eabi_attribute 36
 ; SC300:  .eabi_attribute 38, 1
-; SC300-NOT:  .eabi_attribute 42
-; SC300-NOT:  .eabi_attribute 44
-; SC300-NOT:  .eabi_attribute 68
 
 ; SC300-FAST-NOT:   .eabi_attribute 19
 ;; Despite there being no FPU, we chose to flush to zero preserving
 ;; sign. This matches what the hardware would do for this architecture
 ;; revision.
 ; SC300-FAST:  .eabi_attribute 20, 2
 ; SC300-FAST-NOT:  .eabi_attribute 21
 ; SC300-FAST-NOT:  .eabi_attribute 22
 ; SC300-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-M4-SOFT:  .cpu cortex-m4
 ; CORTEX-M4-SOFT:  .eabi_attribute 6, 13
 ; CORTEX-M4-SOFT:  .eabi_attribute 7, 77
 ; CORTEX-M4-SOFT:  .eabi_attribute 8, 0
 ; CORTEX-M4-SOFT:  .eabi_attribute 9, 2
 ; CORTEX-M4-SOFT:  .fpu fpv4-sp-d16
+; CORTEX-M4-SOFT:  .eabi_attribute 27, 1
+; CORTEX-M4-SOFT:  .eabi_attribute 36, 1
+; CORTEX-M4-SOFT-NOT:  .eabi_attribute 42
+; CORTEX-M4-SOFT-NOT:  .eabi_attribute 44
+; CORTEX-M4-SOFT-NOT:  .eabi_attribute 68
 ; CORTEX-M4-SOFT-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M4-SOFT:  .eabi_attribute 20, 1
 ; CORTEX-M4-SOFT:  .eabi_attribute 21, 1
 ; CORTEX-M4-SOFT-NOT:  .eabi_attribute 22
 ; CORTEX-M4-SOFT:  .eabi_attribute 23, 3
 ; CORTEX-M4-SOFT:  .eabi_attribute 24, 1
 ; CORTEX-M4-SOFT:  .eabi_attribute 25, 1
-; CORTEX-M4-SOFT:  .eabi_attribute 27, 1
 ; CORTEX-M4-SOFT-NOT:  .eabi_attribute 28
-; CORTEX-M4-SOFT:  .eabi_attribute 36, 1
 ; CORTEX-M4-SOFT:  .eabi_attribute 38, 1
-; CORTEX-M4-SOFT-NOT:  .eabi_attribute 42
-; CORTEX-M4-SOFT-NOT:  .eabi_attribute 44
-; CORTEX-M4-SOFT-NOT:  .eabi_attribute 68
 
 ; CORTEX-M4-SOFT-FAST-NOT:   .eabi_attribute 19
 ;; The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when
 ;; -ffast-math is specified.
 ; CORTEX-M4-SOFT-FAST:  .eabi_attribute 20, 2
 ; CORTEX-M4-SOFT-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-M4-SOFT-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-M4-SOFT-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-M4-HARD:  .cpu cortex-m4
 ; CORTEX-M4-HARD:  .eabi_attribute 6, 13
 ; CORTEX-M4-HARD:  .eabi_attribute 7, 77
 ; CORTEX-M4-HARD:  .eabi_attribute 8, 0
 ; CORTEX-M4-HARD:  .eabi_attribute 9, 2
 ; CORTEX-M4-HARD:  .fpu fpv4-sp-d16
+; CORTEX-M4-HARD:  .eabi_attribute 27, 1
+; CORTEX-M4-HARD:  .eabi_attribute 36, 1
+; CORTEX-M4-HARD-NOT:  .eabi_attribute 42
+; CORTEX-M4-HARD-NOT:  .eabi_attribute 44
+; CORTEX-M4-HARD-NOT:  .eabi_attribute 68
 ; CORTEX-M4-HARD-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M4-HARD:  .eabi_attribute 20, 1
 ; CORTEX-M4-HARD:  .eabi_attribute 21, 1
 ; CORTEX-M4-HARD-NOT:  .eabi_attribute 22
 ; CORTEX-M4-HARD:  .eabi_attribute 23, 3
 ; CORTEX-M4-HARD:  .eabi_attribute 24, 1
 ; CORTEX-M4-HARD:  .eabi_attribute 25, 1
-; CORTEX-M4-HARD:  .eabi_attribute 27, 1
 ; CORTEX-M4-HARD:  .eabi_attribute 28, 1
-; CORTEX-M4-HARD:  .eabi_attribute 36, 1
 ; CORTEX-M4-HARD:  .eabi_attribute 38, 1
-; CORTEX-M4-HARD-NOT:  .eabi_attribute 42
-; CORTEX-M4-HARD-NOT:  .eabi_attribute 44
-; CORTEX-M4-HARD-NOT:  .eabi_attribute 68
 
 ; CORTEX-M4-HARD-FAST-NOT:   .eabi_attribute 19
 ;; The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when
 ;; -ffast-math is specified.
 ; CORTEX-M4-HARD-FAST:  .eabi_attribute 20, 2
 ; CORTEX-M4-HARD-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-M4-HARD-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-M4-HARD-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-M7:  .cpu    cortex-m7
 ; CORTEX-M7:  .eabi_attribute 6, 13
 ; CORTEX-M7:  .eabi_attribute 7, 77
 ; CORTEX-M7:  .eabi_attribute 8, 0
 ; CORTEX-M7:  .eabi_attribute 9, 2
 ; CORTEX-M7-SOFT-NOT: .fpu
 ; CORTEX-M7-SINGLE:  .fpu fpv5-sp-d16
 ; CORTEX-M7-DOUBLE:  .fpu fpv5-d16
+; CORTEX-M7-SOFT-NOT: .eabi_attribute 27
+; CORTEX-M7-SINGLE:  .eabi_attribute 27, 1
+; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27
+; CORTEX-M7:  .eabi_attribute 36, 1
+; CORTEX-M7-NOT:  .eabi_attribute 44
 ; CORTEX-M7:  .eabi_attribute 17, 1
 ; CORTEX-M7-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M7:  .eabi_attribute 20, 1
 ; CORTEX-M7:  .eabi_attribute 21, 1
 ; CORTEX-M7-NOT:  .eabi_attribute 22
 ; CORTEX-M7:  .eabi_attribute 23, 3
 ; CORTEX-M7:  .eabi_attribute 24, 1
 ; CORTEX-M7:  .eabi_attribute 25, 1
-; CORTEX-M7-SOFT-NOT: .eabi_attribute 27
-; CORTEX-M7-SINGLE:  .eabi_attribute 27, 1
-; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27
-; CORTEX-M7:  .eabi_attribute 36, 1
 ; CORTEX-M7:  .eabi_attribute 38, 1
-; CORTEX-M7-NOT:  .eabi_attribute 44
 ; CORTEX-M7:  .eabi_attribute 14, 0
 
 ; CORTEX-M7-NOFPU-FAST-NOT:   .eabi_attribute 19
 ;; The M7 has the ARMv8 FP unit, which always flushes preserving sign.
 ; CORTEX-M7-FAST:  .eabi_attribute 20, 2
 ;; Despite there being no FPU, we chose to flush to zero preserving
 ;; sign. This matches what the hardware would do for this architecture
 ;; revision.
 ; CORTEX-M7-NOFPU-FAST: .eabi_attribute 20, 2
 ; CORTEX-M7-NOFPU-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-M7-NOFPU-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-M7-NOFPU-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-R4:  .cpu cortex-r4
 ; CORTEX-R4:  .eabi_attribute 6, 10
 ; CORTEX-R4:  .eabi_attribute 7, 82
 ; CORTEX-R4:  .eabi_attribute 8, 1
 ; CORTEX-R4:  .eabi_attribute 9, 2
 ; CORTEX-R4-NOT:  .fpu vfpv3-d16
+; CORTEX-R4-NOT:  .eabi_attribute 36
+; CORTEX-R4-NOT:  .eabi_attribute 42
+; CORTEX-R4-NOT:  .eabi_attribute 44
+; CORTEX-R4-NOT:  .eabi_attribute 68
 ; CORTEX-R4-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-R4:  .eabi_attribute 20, 1
 ; CORTEX-R4:  .eabi_attribute 21, 1
 ; CORTEX-R4-NOT:  .eabi_attribute 22
 ; CORTEX-R4:  .eabi_attribute 23, 3
 ; CORTEX-R4:  .eabi_attribute 24, 1
 ; CORTEX-R4:  .eabi_attribute 25, 1
 ; CORTEX-R4-NOT:  .eabi_attribute 28
-; CORTEX-R4-NOT:  .eabi_attribute 36
 ; CORTEX-R4:  .eabi_attribute 38, 1
-; CORTEX-R4-NOT:  .eabi_attribute 42
-; CORTEX-R4-NOT:  .eabi_attribute 44
-; CORTEX-R4-NOT:  .eabi_attribute 68
 
 ; CORTEX-R4F:  .cpu cortex-r4f
 ; CORTEX-R4F:  .eabi_attribute 6, 10
 ; CORTEX-R4F:  .eabi_attribute 7, 82
 ; CORTEX-R4F:  .eabi_attribute 8, 1
 ; CORTEX-R4F:  .eabi_attribute 9, 2
 ; CORTEX-R4F:  .fpu vfpv3-d16
+; CORTEX-R4F-NOT:  .eabi_attribute 27, 1
+; CORTEX-R4F-NOT:  .eabi_attribute 36
+; CORTEX-R4F-NOT:  .eabi_attribute 42
+; CORTEX-R4F-NOT:  .eabi_attribute 44
+; CORTEX-R4F-NOT:  .eabi_attribute 68
 ; CORTEX-R4F-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-R4F:  .eabi_attribute 20, 1
 ; CORTEX-R4F:  .eabi_attribute 21, 1
 ; CORTEX-R4F-NOT:  .eabi_attribute 22
 ; CORTEX-R4F:  .eabi_attribute 23, 3
 ; CORTEX-R4F:  .eabi_attribute 24, 1
 ; CORTEX-R4F:  .eabi_attribute 25, 1
-; CORTEX-R4F-NOT:  .eabi_attribute 27, 1
 ; CORTEX-R4F-NOT:  .eabi_attribute 28
-; CORTEX-R4F-NOT:  .eabi_attribute 36
 ; CORTEX-R4F:  .eabi_attribute 38, 1
-; CORTEX-R4F-NOT:  .eabi_attribute 42
-; CORTEX-R4F-NOT:  .eabi_attribute 44
-; CORTEX-R4F-NOT:  .eabi_attribute 68
 
 ; CORTEX-R5:  .cpu cortex-r5
 ; CORTEX-R5:  .eabi_attribute 6, 10
 ; CORTEX-R5:  .eabi_attribute 7, 82
 ; CORTEX-R5:  .eabi_attribute 8, 1
 ; CORTEX-R5:  .eabi_attribute 9, 2
 ; CORTEX-R5:  .fpu vfpv3-d16
+; CORTEX-R5-NOT:  .eabi_attribute 27, 1
+; CORTEX-R5-NOT:  .eabi_attribute 36
+; CORTEX-R5:  .eabi_attribute 44, 2
+; CORTEX-R5-NOT:  .eabi_attribute 42
+; CORTEX-R5-NOT:  .eabi_attribute 68
 ; CORTEX-R5-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-R5:  .eabi_attribute 20, 1
 ; CORTEX-R5:  .eabi_attribute 21, 1
 ; CORTEX-R5-NOT:  .eabi_attribute 22
 ; CORTEX-R5:  .eabi_attribute 23, 3
 ; CORTEX-R5:  .eabi_attribute 24, 1
 ; CORTEX-R5:  .eabi_attribute 25, 1
-; CORTEX-R5-NOT:  .eabi_attribute 27, 1
 ; CORTEX-R5-NOT:  .eabi_attribute 28
-; CORTEX-R5-NOT:  .eabi_attribute 36
 ; CORTEX-R5:  .eabi_attribute 38, 1
-; CORTEX-R5-NOT:  .eabi_attribute 42
-; CORTEX-R5:  .eabi_attribute 44, 2
-; CORTEX-R5-NOT:  .eabi_attribute 68
 
 ; CORTEX-R5-FAST-NOT:   .eabi_attribute 19
 ;; The R5 has the VFPv3 FP unit, which always flushes preserving sign.
 ; CORTEX-R5-FAST:  .eabi_attribute 20, 2
 ; CORTEX-R5-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-R5-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-R5-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-R7:  .cpu cortex-r7
 ; CORTEX-R7:  .eabi_attribute 6, 10
 ; CORTEX-R7:  .eabi_attribute 7, 82
 ; CORTEX-R7:  .eabi_attribute 8, 1
 ; CORTEX-R7:  .eabi_attribute 9, 2
 ; CORTEX-R7:  .fpu vfpv3-d16-fp16
+; CORTEX-R7:  .eabi_attribute 36, 1
+; CORTEX-R7:  .eabi_attribute 42, 1
+; CORTEX-R7:  .eabi_attribute 44, 2
+; CORTEX-R7-NOT:  .eabi_attribute 68
 ; CORTEX-R7-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-R7:  .eabi_attribute 20, 1
 ; CORTEX-R7:  .eabi_attribute 21, 1
 ; CORTEX-R7-NOT:  .eabi_attribute 22
 ; CORTEX-R7:  .eabi_attribute 23, 3
 ; CORTEX-R7:  .eabi_attribute 24, 1
 ; CORTEX-R7:  .eabi_attribute 25, 1
 ; CORTEX-R7-NOT:  .eabi_attribute 28
-; CORTEX-R7:  .eabi_attribute 36, 1
 ; CORTEX-R7:  .eabi_attribute 38, 1
-; CORTEX-R7:  .eabi_attribute 42, 1
-; CORTEX-R7:  .eabi_attribute 44, 2
-; CORTEX-R7-NOT:  .eabi_attribute 68
 
 ; CORTEX-R7-FAST-NOT:   .eabi_attribute 19
 ;; The R7 has the VFPv3 FP unit, which always flushes preserving sign.
 ; CORTEX-R7-FAST:  .eabi_attribute 20, 2
 ; CORTEX-R7-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-R7-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-R7-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-R8:  .cpu cortex-r8
 ; CORTEX-R8:  .eabi_attribute 6, 10
 ; CORTEX-R8:  .eabi_attribute 7, 82
 ; CORTEX-R8:  .eabi_attribute 8, 1
 ; CORTEX-R8:  .eabi_attribute 9, 2
 ; CORTEX-R8:  .fpu vfpv3-d16-fp16
+; CORTEX-R8:  .eabi_attribute 36, 1
+; CORTEX-R8:  .eabi_attribute 42, 1
+; CORTEX-R8:  .eabi_attribute 44, 2
+; CORTEX-R8-NOT:  .eabi_attribute 68
 ; CORTEX-R8-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-R8:  .eabi_attribute 20, 1
 ; CORTEX-R8:  .eabi_attribute 21, 1
 ; CORTEX-R8-NOT:  .eabi_attribute 22
 ; CORTEX-R8:  .eabi_attribute 23, 3
 ; CORTEX-R8:  .eabi_attribute 24, 1
 ; CORTEX-R8:  .eabi_attribute 25, 1
 ; CORTEX-R8-NOT:  .eabi_attribute 28
-; CORTEX-R8:  .eabi_attribute 36, 1
 ; CORTEX-R8:  .eabi_attribute 38, 1
-; CORTEX-R8:  .eabi_attribute 42, 1
-; CORTEX-R8:  .eabi_attribute 44, 2
-; CORTEX-R8-NOT:  .eabi_attribute 68
 
 ; CORTEX-R8-FAST-NOT:   .eabi_attribute 19
 ;; The R8 has the VFPv3 FP unit, which always flushes preserving sign.
 ; CORTEX-R8-FAST:  .eabi_attribute 20, 2
 ; CORTEX-R8-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-R8-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-R8-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-A32:  .cpu cortex-a32
 ; CORTEX-A32:  .eabi_attribute 6, 14
 ; CORTEX-A32:  .eabi_attribute 7, 65
 ; CORTEX-A32:  .eabi_attribute 8, 1
 ; CORTEX-A32:  .eabi_attribute 9, 2
 ; CORTEX-A32:  .fpu crypto-neon-fp-armv8
 ; CORTEX-A32:  .eabi_attribute 12, 3
+; CORTEX-A32-NOT:  .eabi_attribute 27
+; CORTEX-A32:  .eabi_attribute 36, 1
+; CORTEX-A32:  .eabi_attribute 42, 1
+; CORTEX-A32-NOT:  .eabi_attribute 44
+; CORTEX-A32:  .eabi_attribute 68, 3
 ; CORTEX-A32-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A32:  .eabi_attribute 20, 1
 ; CORTEX-A32:  .eabi_attribute 21, 1
 ; CORTEX-A32-NOT:  .eabi_attribute 22
 ; CORTEX-A32:  .eabi_attribute 23, 3
 ; CORTEX-A32:  .eabi_attribute 24, 1
 ; CORTEX-A32:  .eabi_attribute 25, 1
-; CORTEX-A32-NOT:  .eabi_attribute 27
 ; CORTEX-A32-NOT:  .eabi_attribute 28
-; CORTEX-A32:  .eabi_attribute 36, 1
 ; CORTEX-A32:  .eabi_attribute 38, 1
-; CORTEX-A32:  .eabi_attribute 42, 1
-; CORTEX-A32-NOT:  .eabi_attribute 44
-; CORTEX-A32:  .eabi_attribute 68, 3
 
 ; CORTEX-A32-FAST-NOT:   .eabi_attribute 19
 ;; The A32 has the ARMv8 FP unit, which always flushes preserving sign.
 ; CORTEX-A32-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A32-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-A32-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A32-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-M23:  .cpu cortex-m23
 ; CORTEX-M23:  .eabi_attribute 6, 16
 ; CORTEX-M23:  .eabi_attribute 7, 77
 ; CORTEX-M23:  .eabi_attribute 8, 0
 ; CORTEX-M23:  .eabi_attribute 9, 3
+; CORTEX-M23-NOT:  .eabi_attribute 27
+; CORTEX-M23:  .eabi_attribute 34, 1
+; CORTEX-M23-NOT:  .eabi_attribute 44
 ; CORTEX-M23:  .eabi_attribute 17, 1
 ;; We default to IEEE 754 compliance
 ; CORTEX-M23-NOT:   .eabi_attribute 19
 ; CORTEX-M23:  .eabi_attribute 20, 1
 ; CORTEX-M23:  .eabi_attribute 21, 1
 ; CORTEX-M23:  .eabi_attribute 23, 3
-; CORTEX-M23:  .eabi_attribute 34, 1
 ; CORTEX-M23:  .eabi_attribute 24, 1
-; CORTEX-M23-NOT:  .eabi_attribute 27
 ; CORTEX-M23-NOT:  .eabi_attribute 28
 ; CORTEX-M23:  .eabi_attribute 25, 1
 ; CORTEX-M23:  .eabi_attribute 38, 1
 ; CORTEX-M23:  .eabi_attribute 14, 0
-; CORTEX-M23-NOT:  .eabi_attribute 44
 
 ; CORTEX-M33:  .cpu cortex-m33
 ; CORTEX-M33:  .eabi_attribute 6, 17
 ; CORTEX-M33:  .eabi_attribute 7, 77
 ; CORTEX-M33:  .eabi_attribute 8, 0
 ; CORTEX-M33:  .eabi_attribute 9, 3
 ; CORTEX-M33:  .fpu fpv5-sp-d16
+; CORTEX-M33:  .eabi_attribute 27, 1
+; CORTEX-M33:  .eabi_attribute 36, 1
+; CORTEX-M33-NOT:  .eabi_attribute 44
+; CORTEX-M33:  .eabi_attribute 46, 1
+; CORTEX-M33:  .eabi_attribute 34, 1
 ; CORTEX-M33:  .eabi_attribute 17, 1
 ;; We default to IEEE 754 compliance
 ; CORTEX-M23-NOT:   .eabi_attribute 19
 ; CORTEX-M33:  .eabi_attribute 20, 1
 ; CORTEX-M33:  .eabi_attribute 21, 1
 ; CORTEX-M33:  .eabi_attribute 23, 3
-; CORTEX-M33:  .eabi_attribute 34, 1
 ; CORTEX-M33:  .eabi_attribute 24, 1
 ; CORTEX-M33:  .eabi_attribute 25, 1
-; CORTEX-M33:  .eabi_attribute 27, 1
 ; CORTEX-M33-NOT:  .eabi_attribute 28
-; CORTEX-M33:  .eabi_attribute 36, 1
 ; CORTEX-M33:  .eabi_attribute 38, 1
-; CORTEX-M33:  .eabi_attribute 46, 1
-; CORTEX-M33-NOT:  .eabi_attribute 44
 ; CORTEX-M33:  .eabi_attribute 14, 0
 
 ; CORTEX-M33-FAST-NOT:   .eabi_attribute 19
 ; CORTEX-M33-FAST:  .eabi_attribute 20, 2
 ; CORTEX-M33-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-M33-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-M33-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-A35:  .cpu cortex-a35
 ; CORTEX-A35:  .eabi_attribute 6, 14
 ; CORTEX-A35:  .eabi_attribute 7, 65
 ; CORTEX-A35:  .eabi_attribute 8, 1
 ; CORTEX-A35:  .eabi_attribute 9, 2
 ; CORTEX-A35:  .fpu crypto-neon-fp-armv8
 ; CORTEX-A35:  .eabi_attribute 12, 3
+; CORTEX-A35-NOT:  .eabi_attribute 27
+; CORTEX-A35:  .eabi_attribute 36, 1
+; CORTEX-A35:  .eabi_attribute 42, 1
+; CORTEX-A35-NOT:  .eabi_attribute 44
+; CORTEX-A35:  .eabi_attribute 68, 3
 ; CORTEX-A35-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A35:  .eabi_attribute 20, 1
 ; CORTEX-A35:  .eabi_attribute 21, 1
 ; CORTEX-A35-NOT:  .eabi_attribute 22
 ; CORTEX-A35:  .eabi_attribute 23, 3
 ; CORTEX-A35:  .eabi_attribute 24, 1
 ; CORTEX-A35:  .eabi_attribute 25, 1
-; CORTEX-A35-NOT:  .eabi_attribute 27
 ; CORTEX-A35-NOT:  .eabi_attribute 28
-; CORTEX-A35:  .eabi_attribute 36, 1
 ; CORTEX-A35:  .eabi_attribute 38, 1
-; CORTEX-A35:  .eabi_attribute 42, 1
-; CORTEX-A35-NOT:  .eabi_attribute 44
-; CORTEX-A35:  .eabi_attribute 68, 3
 
 ; CORTEX-A35-FAST-NOT:   .eabi_attribute 19
 ;; The A35 has the ARMv8 FP unit, which always flushes preserving sign.
 ; CORTEX-A35-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A35-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-A35-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A35-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-A53:  .cpu cortex-a53
 ; CORTEX-A53:  .eabi_attribute 6, 14
 ; CORTEX-A53:  .eabi_attribute 7, 65
 ; CORTEX-A53:  .eabi_attribute 8, 1
 ; CORTEX-A53:  .eabi_attribute 9, 2
 ; CORTEX-A53:  .fpu crypto-neon-fp-armv8
 ; CORTEX-A53:  .eabi_attribute 12, 3
+; CORTEX-A53-NOT:  .eabi_attribute 27
+; CORTEX-A53:  .eabi_attribute 36, 1
+; CORTEX-A53:  .eabi_attribute 42, 1
+; CORTEX-A53-NOT:  .eabi_attribute 44
+; CORTEX-A53:  .eabi_attribute 68, 3
 ; CORTEX-A53-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A53:  .eabi_attribute 20, 1
 ; CORTEX-A53:  .eabi_attribute 21, 1
 ; CORTEX-A53-NOT:  .eabi_attribute 22
 ; CORTEX-A53:  .eabi_attribute 23, 3
 ; CORTEX-A53:  .eabi_attribute 24, 1
 ; CORTEX-A53:  .eabi_attribute 25, 1
-; CORTEX-A53-NOT:  .eabi_attribute 27
 ; CORTEX-A53-NOT:  .eabi_attribute 28
-; CORTEX-A53:  .eabi_attribute 36, 1
 ; CORTEX-A53:  .eabi_attribute 38, 1
-; CORTEX-A53:  .eabi_attribute 42, 1
-; CORTEX-A53-NOT:  .eabi_attribute 44
-; CORTEX-A53:  .eabi_attribute 68, 3
 
 ; CORTEX-A53-FAST-NOT:   .eabi_attribute 19
 ;; The A53 has the ARMv8 FP unit, which always flushes preserving sign.
 ; CORTEX-A53-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A53-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-A53-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A53-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-A57:  .cpu cortex-a57
 ; CORTEX-A57:  .eabi_attribute 6, 14
 ; CORTEX-A57:  .eabi_attribute 7, 65
 ; CORTEX-A57:  .eabi_attribute 8, 1
 ; CORTEX-A57:  .eabi_attribute 9, 2
 ; CORTEX-A57:  .fpu crypto-neon-fp-armv8
 ; CORTEX-A57:  .eabi_attribute 12, 3
+; CORTEX-A57-NOT:  .eabi_attribute 27
+; CORTEX-A57:  .eabi_attribute 36, 1
+; CORTEX-A57:  .eabi_attribute 42, 1
+; CORTEX-A57-NOT:  .eabi_attribute 44
+; CORTEX-A57:  .eabi_attribute 68, 3
 ; CORTEX-A57-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A57:  .eabi_attribute 20, 1
 ; CORTEX-A57:  .eabi_attribute 21, 1
 ; CORTEX-A57-NOT:  .eabi_attribute 22
 ; CORTEX-A57:  .eabi_attribute 23, 3
 ; CORTEX-A57:  .eabi_attribute 24, 1
 ; CORTEX-A57:  .eabi_attribute 25, 1
-; CORTEX-A57-NOT:  .eabi_attribute 27
 ; CORTEX-A57-NOT:  .eabi_attribute 28
-; CORTEX-A57:  .eabi_attribute 36, 1
 ; CORTEX-A57:  .eabi_attribute 38, 1
-; CORTEX-A57:  .eabi_attribute 42, 1
-; CORTEX-A57-NOT:  .eabi_attribute 44
-; CORTEX-A57:  .eabi_attribute 68, 3
 
 ; CORTEX-A57-FAST-NOT:   .eabi_attribute 19
 ;; The A57 has the ARMv8 FP unit, which always flushes preserving sign.
 ; CORTEX-A57-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A57-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-A57-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A57-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-A72:  .cpu cortex-a72
 ; CORTEX-A72:  .eabi_attribute 6, 14
 ; CORTEX-A72:  .eabi_attribute 7, 65
 ; CORTEX-A72:  .eabi_attribute 8, 1
 ; CORTEX-A72:  .eabi_attribute 9, 2
 ; CORTEX-A72:  .fpu crypto-neon-fp-armv8
 ; CORTEX-A72:  .eabi_attribute 12, 3
+; CORTEX-A72-NOT:  .eabi_attribute 27
+; CORTEX-A72:  .eabi_attribute 36, 1
+; CORTEX-A72:  .eabi_attribute 42, 1
+; CORTEX-A72-NOT:  .eabi_attribute 44
+; CORTEX-A72:  .eabi_attribute 68, 3
 ; CORTEX-A72-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A72:  .eabi_attribute 20, 1
 ; CORTEX-A72:  .eabi_attribute 21, 1
 ; CORTEX-A72-NOT:  .eabi_attribute 22
 ; CORTEX-A72:  .eabi_attribute 23, 3
 ; CORTEX-A72:  .eabi_attribute 24, 1
 ; CORTEX-A72:  .eabi_attribute 25, 1
-; CORTEX-A72-NOT:  .eabi_attribute 27
 ; CORTEX-A72-NOT:  .eabi_attribute 28
-; CORTEX-A72:  .eabi_attribute 36, 1
 ; CORTEX-A72:  .eabi_attribute 38, 1
-; CORTEX-A72:  .eabi_attribute 42, 1
-; CORTEX-A72-NOT:  .eabi_attribute 44
-; CORTEX-A72:  .eabi_attribute 68, 3
 
 ; CORTEX-A72-FAST-NOT:   .eabi_attribute 19
 ;; The A72 has the ARMv8 FP unit, which always flushes preserving sign.
 ; CORTEX-A72-FAST:  .eabi_attribute 20, 2
 ; CORTEX-A72-FAST-NOT:  .eabi_attribute 21
 ; CORTEX-A72-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-A72-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-A73:  .cpu cortex-a73
 ; CORTEX-A73:  .eabi_attribute 6, 14
 ; CORTEX-A73:  .eabi_attribute 7, 65
 ; CORTEX-A73:  .eabi_attribute 8, 1
 ; CORTEX-A73:  .eabi_attribute 9, 2
 ; CORTEX-A73:  .fpu  crypto-neon-fp-armv8
 ; CORTEX-A73:  .eabi_attribute 12, 3
+; CORTEX-A73-NOT: .eabi_attribute 27
+; CORTEX-A73:  .eabi_attribute 36, 1
+; CORTEX-A73:  .eabi_attribute 42, 1
+; CORTEX-A73-NOT: .eabi_attribute 44
+; CORTEX-A73:  .eabi_attribute 68, 3
 ; CORTEX-A73-NOT: .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A73:  .eabi_attribute 20, 1
 ; CORTEX-A73:  .eabi_attribute 21, 1
 ; CORTEX-A73-NOT:  .eabi_attribute 22
 ; CORTEX-A73:  .eabi_attribute 23, 3
 ; CORTEX-A73:  .eabi_attribute 24, 1
 ; CORTEX-A73:  .eabi_attribute 25, 1
-; CORTEX-A73-NOT: .eabi_attribute 27
 ; CORTEX-A73-NOT: .eabi_attribute 28
-; CORTEX-A73:  .eabi_attribute 36, 1
 ; CORTEX-A73:  .eabi_attribute 38, 1
-; CORTEX-A73:  .eabi_attribute 42, 1
-; CORTEX-A73-NOT: .eabi_attribute 44
 ; CORTEX-A73:  .eabi_attribute 14, 0
-; CORTEX-A73:  .eabi_attribute 68, 3
 
 ; EXYNOS-M1:  .cpu exynos-m1
 ; EXYNOS-M1:  .eabi_attribute 6, 14
 ; EXYNOS-M1:  .eabi_attribute 7, 65
 ; EXYNOS-M1:  .eabi_attribute 8, 1
 ; EXYNOS-M1:  .eabi_attribute 9, 2
 ; EXYNOS-M1:  .fpu crypto-neon-fp-armv8
 ; EXYNOS-M1:  .eabi_attribute 12, 3
+; EXYNOS-M1-NOT:  .eabi_attribute 27
+; EXYNOS-M1:  .eabi_attribute 36, 1
+; EXYNOS-M1:  .eabi_attribute 42, 1
+; EXYNOS-M1-NOT:  .eabi_attribute 44
+; EXYNOS-M1:  .eabi_attribute 68, 3
 ; EXYNOS-M1-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; EXYNOS-M1:  .eabi_attribute 20, 1
 ; EXYNOS-M1:  .eabi_attribute 21, 1
 ; EXYNOS-M1-NOT:  .eabi_attribute 22
 ; EXYNOS-M1:  .eabi_attribute 23, 3
 ; EXYNOS-M1:  .eabi_attribute 24, 1
 ; EXYNOS-M1:  .eabi_attribute 25, 1
-; EXYNOS-M1-NOT:  .eabi_attribute 27
 ; EXYNOS-M1-NOT:  .eabi_attribute 28
-; EXYNOS-M1:  .eabi_attribute 36, 1
 ; EXYNOS-M1:  .eabi_attribute 38, 1
-; EXYNOS-M1:  .eabi_attribute 42, 1
-; EXYNOS-M1-NOT:  .eabi_attribute 44
-; EXYNOS-M1:  .eabi_attribute 68, 3
 
 ; EXYNOS-M1-FAST-NOT:   .eabi_attribute 19
 ;; The exynos-m1 has the ARMv8 FP unit, which always flushes preserving sign.
 ; EXYNOS-M1-FAST:  .eabi_attribute 20, 2
 ; EXYNOS-M1-FAST-NOT:  .eabi_attribute 21
 ; EXYNOS-M1-FAST-NOT:  .eabi_attribute 22
 ; EXYNOS-M1-FAST:  .eabi_attribute 23, 1
 
 ; EXYNOS-M2:  .cpu exynos-m2
 ; EXYNOS-M2:  .eabi_attribute 6, 14
 ; EXYNOS-M2:  .eabi_attribute 7, 65
 ; EXYNOS-M2:  .eabi_attribute 8, 1
 ; EXYNOS-M2:  .eabi_attribute 9, 2
 ; EXYNOS-M2:  .fpu crypto-neon-fp-armv8
 ; EXYNOS-M2:  .eabi_attribute 12, 3
+; EXYNOS-M2-NOT:  .eabi_attribute 27
+; EXYNOS-M2:  .eabi_attribute 36, 1
+; EXYNOS-M2:  .eabi_attribute 42, 1
+; EXYNOS-M2-NOT:  .eabi_attribute 44
+; EXYNOS-M2:  .eabi_attribute 68, 3
 ; EXYNOS-M2-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; EXYNOS-M2:  .eabi_attribute 20, 1
 ; EXYNOS-M2:  .eabi_attribute 21, 1
 ; EXYNOS-M2-NOT:  .eabi_attribute 22
 ; EXYNOS-M2:  .eabi_attribute 23, 3
 ; EXYNOS-M2:  .eabi_attribute 24, 1
 ; EXYNOS-M2:  .eabi_attribute 25, 1
-; EXYNOS-M2-NOT:  .eabi_attribute 27
 ; EXYNOS-M2-NOT:  .eabi_attribute 28
-; EXYNOS-M2:  .eabi_attribute 36, 1
 ; EXYNOS-M2:  .eabi_attribute 38, 1
-; EXYNOS-M2:  .eabi_attribute 42, 1
-; EXYNOS-M2-NOT:  .eabi_attribute 44
-; EXYNOS-M2:  .eabi_attribute 68, 3
 
 ; EXYNOS-M3:  .cpu exynos-m3
 ; EXYNOS-M3:  .eabi_attribute 6, 14
 ; EXYNOS-M3:  .eabi_attribute 7, 65
 ; EXYNOS-M3:  .eabi_attribute 8, 1
 ; EXYNOS-M3:  .eabi_attribute 9, 2
 ; EXYNOS-M3:  .fpu crypto-neon-fp-armv8
 ; EXYNOS-M3:  .eabi_attribute 12, 3
+; EXYNOS-M3-NOT:  .eabi_attribute 27
+; EXYNOS-M3:  .eabi_attribute 36, 1
+; EXYNOS-M3:  .eabi_attribute 42, 1
+; EXYNOS-M3-NOT:  .eabi_attribute 44
+; EXYNOS-M3:  .eabi_attribute 68, 3
 ; EXYNOS-M3-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; EXYNOS-M3:  .eabi_attribute 20, 1
 ; EXYNOS-M3:  .eabi_attribute 21, 1
 ; EXYNOS-M3-NOT:  .eabi_attribute 22
 ; EXYNOS-M3:  .eabi_attribute 23, 3
 ; EXYNOS-M3:  .eabi_attribute 24, 1
 ; EXYNOS-M3:  .eabi_attribute 25, 1
-; EXYNOS-M3-NOT:  .eabi_attribute 27
 ; EXYNOS-M3-NOT:  .eabi_attribute 28
-; EXYNOS-M3:  .eabi_attribute 36, 1
 ; EXYNOS-M3:  .eabi_attribute 38, 1
-; EXYNOS-M3:  .eabi_attribute 42, 1
-; EXYNOS-M3-NOT:  .eabi_attribute 44
-; EXYNOS-M3:  .eabi_attribute 68, 3
 
 ; GENERIC-FPU-VFPV3-FP16: .fpu vfpv3-fp16
 ; GENERIC-FPU-VFPV3-D16-FP16: .fpu vfpv3-d16-fp16
 ; GENERIC-FPU-VFPV3XD: .fpu vfpv3xd
 ; GENERIC-FPU-VFPV3XD-FP16: .fpu vfpv3xd-fp16
 ; GENERIC-FPU-NEON-FP16: .fpu neon-fp16
 
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 6, 14
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 7, 65
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 8, 1
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 9, 2
 ; GENERIC-ARMV8_1-A:  .fpu crypto-neon-fp-armv8
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 12, 4
+; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 27
+; GENERIC-ARMV8_1-A:  .eabi_attribute 36, 1
+; GENERIC-ARMV8_1-A:  .eabi_attribute 42, 1
+; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 44
+; GENERIC-ARMV8_1-A:  .eabi_attribute 68, 3
 ; GENERIC-ARMV8_1-A-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 20, 1
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 21, 1
 ; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 22
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 23, 3
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 24, 1
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 25, 1
-; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 27
 ; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 28
-; GENERIC-ARMV8_1-A:  .eabi_attribute 36, 1
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 38, 1
-; GENERIC-ARMV8_1-A:  .eabi_attribute 42, 1
-; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 44
-; GENERIC-ARMV8_1-A:  .eabi_attribute 68, 3
 
 ; GENERIC-ARMV8_1-A-FAST-NOT:   .eabi_attribute 19
 ;; GENERIC-ARMV8_1-A has the ARMv8 FP unit, which always flushes preserving sign.
 ; GENERIC-ARMV8_1-A-FAST:  .eabi_attribute 20, 2
 ; GENERIC-ARMV8_1-A-FAST-NOT:  .eabi_attribute 21
 ; GENERIC-ARMV8_1-A-FAST-NOT:  .eabi_attribute 22
 ; GENERIC-ARMV8_1-A-FAST:  .eabi_attribute 23, 1
 

 ; ARMv8R: .eabi_attribute 8, 1    @ Tag_ARM_ISA_use
 ; ARMv8R: .eabi_attribute 9, 2    @ Tag_THUMB_ISA_use
 ; ARMv8R-NOFPU-NOT: .fpu
 ; ARMv8R-NOFPU-NOT: .eabi_attribute 12
 ; ARMv8R-SP: .fpu fpv5-sp-d16
 ; ARMv8R-SP-NOT: .eabi_attribute 12
 ; ARMv8R-NEON: .fpu    neon-fp-armv8
 ; ARMv8R-NEON: .eabi_attribute 12, 3   @ Tag_Advanced_SIMD_arch
-; ARMv8R: .eabi_attribute 17, 1   @ Tag_ABI_PCS_GOT_use
-; ARMv8R: .eabi_attribute 20, 1   @ Tag_ABI_FP_denormal
-; ARMv8R: .eabi_attribute 21, 1   @ Tag_ABI_FP_exceptions
-; ARMv8R: .eabi_attribute 23, 3   @ Tag_ABI_FP_number_model
-; ARMv8R: .eabi_attribute 34, 1   @ Tag_CPU_unaligned_access
-; ARMv8R: .eabi_attribute 24, 1   @ Tag_ABI_align_needed
-; ARMv8R: .eabi_attribute 25, 1   @ Tag_ABI_align_preserved
 ; ARMv8R-NOFPU-NOT: .eabi_attribute 27
 ; ARMv8R-SP: .eabi_attribute 27, 1   @ Tag_ABI_HardFP_use
 ; ARMv8R-NEON-NOT: .eabi_attribute 27
 ; ARMv8R-NOFPU-NOT: .eabi_attribute 36
 ; ARMv8R-SP: .eabi_attribute 36, 1   @ Tag_FP_HP_extension
 ; ARMv8R-NEON: .eabi_attribute 36, 1   @ Tag_FP_HP_extension
-; ARMv8R: .eabi_attribute 38, 1   @ Tag_ABI_FP_16bit_format
 ; ARMv8R: .eabi_attribute 42, 1   @ Tag_MPextension_use
-; ARMv8R: .eabi_attribute 14, 0   @ Tag_ABI_PCS_R9_use
 ; ARMv8R: .eabi_attribute 68, 2   @ Tag_Virtualization_use
+; ARMv8R: .eabi_attribute 38, 1   @ Tag_ABI_FP_16bit_format
+; ARMv8R: .eabi_attribute 14, 0   @ Tag_ABI_PCS_R9_use
 
 define i32 @f(i64 %z) {
     ret i32 0
 }

test/MC/ARM/assmebly-default-build-attributes.s

+// RUN: llvm-mc -triple armv7a < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v7A
+// RUN: llvm-mc -triple armv6m < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v6M
+// RUN: llvm-mc -triple armv7m < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v7M
+// RUN: llvm-mc -triple armv7a -mcpu=cortex-a15 < %s -arm-add-build-attributes | FileCheck %s --check-prefix=Cortex-A15
+
+// This isn't intended to be a through check of the build attributes emitted
+// for each target (that's tested elsewhere), but just to check that the
+// hardware attributes are emitted by the assembler based on the selected
+// target when requested.
+
+// v7A-NOT: .cpu
+// v7A: .eabi_attribute 6, 10   @ Tag_CPU_arch
+// v7A: .eabi_attribute 7, 65   @ Tag_CPU_arch_profile
+// v7A: .eabi_attribute 8, 1    @ Tag_ARM_ISA_use
+// v7A: .eabi_attribute 9, 2    @ Tag_THUMB_ISA_use
+// v7A: .fpu    neon
+// v7A: .eabi_attribute 34, 1   @ Tag_CPU_unaligned_access
+
+// v6M-NOT: .cpu
+// v6M: .eabi_attribute 6, 12   @ Tag_CPU_arch
+// v6M: .eabi_attribute 7, 77   @ Tag_CPU_arch_profile
+// v6M: .eabi_attribute 8, 0    @ Tag_ARM_ISA_use
+// v6M: .eabi_attribute 9, 1    @ Tag_THUMB_ISA_use
+// v6M: .eabi_attribute 34, 1   @ Tag_CPU_unaligned_access
+
+// v7M-NOT: .cpu
+// v7M: .eabi_attribute 6, 10   @ Tag_CPU_arch
+// v7M: .eabi_attribute 7, 77   @ Tag_CPU_arch_profile
+// v7M: .eabi_attribute 8, 0    @ Tag_ARM_ISA_use
+// v7M: .eabi_attribute 9, 2    @ Tag_THUMB_ISA_use
+// v7M: .eabi_attribute 34, 1   @ Tag_CPU_unaligned_access
+
+// Cortex-A15: .cpu    cortex-a15
+// Cortex-A15: .eabi_attribute 6, 10   @ Tag_CPU_arch
+// Cortex-A15: .eabi_attribute 7, 65   @ Tag_CPU_arch_profile
+// Cortex-A15: .eabi_attribute 8, 1    @ Tag_ARM_ISA_use
+// Cortex-A15: .eabi_attribute 9, 2    @ Tag_THUMB_ISA_use
+// Cortex-A15: .fpu    neon-vfpv4
+// Cortex-A15: .eabi_attribute 36, 1   @ Tag_FP_HP_extension
+// Cortex-A15: .eabi_attribute 42, 1   @ Tag_MPextension_use
+// Cortex-A15: .eabi_attribute 44, 2   @ Tag_DIV_use
+// Cortex-A15: .eabi_attribute 34, 1   @ Tag_CPU_unaligned_access
+// Cortex-A15: .eabi_attribute 68, 3   @ Tag_Virtualization_use