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Differential D31810

[AMDGPU][MC] Fix for bug 32552 + LIT tests
ClosedPublic

Authored by dp on Apr 7 2017, 8:21 AM.

Details

Reviewers
vpykhtin
Commits
rG3bff0c8c595f: [AMDGPU][MC] Corrected encoding of V_MQSAD_U32_U8 for CI
rL300070: [AMDGPU][MC] Corrected encoding of V_MQSAD_U32_U8 for CI
Summary

Corrected encoding of V_MQSAD_U32_U8 for CI

Diff Detail

Repository
rL LLVM

Event Timeline

dp created this revision.Apr 7 2017, 8:21 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptApr 7 2017, 8:21 AM
vpykhtin accepted this revision.Apr 12 2017, 3:48 AM

LGTM.

This revision is now accepted and ready to land.Apr 12 2017, 3:48 AM
Closed by commit rL300070: [AMDGPU][MC] Corrected encoding of V_MQSAD_U32_U8 for CI (authored by dpreobra). · Explain WhyApr 12 2017, 8:48 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
2 lines
test/
MC/
AMDGPU/
2 lines

Diff 94977

llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td

Show First 20 Lines • Show All 396 Lines • ▼ Show 20 Lines def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> { VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
let AssemblerPredicates = [isCIOnly]; let AssemblerPredicates = [isCIOnly];
let DecoderNamespace = "CI"; let DecoderNamespace = "CI";
} }
} }
defm V_MQSAD_U16_U8 : VOP3_Real_ci <0x172>; defm V_MQSAD_U16_U8 : VOP3_Real_ci <0x172>;
defm V_QSAD_PK_U16_U8 : VOP3_Real_ci <0x172>; defm V_QSAD_PK_U16_U8 : VOP3_Real_ci <0x172>;
defm V_MQSAD_U32_U8 : VOP3_Real_ci <0x174>; defm V_MQSAD_U32_U8 : VOP3_Real_ci <0x175>;
defm V_MAD_U64_U32 : VOP3be_Real_ci <0x176>; defm V_MAD_U64_U32 : VOP3be_Real_ci <0x176>;
defm V_MAD_I64_I32 : VOP3be_Real_ci <0x177>; defm V_MAD_I64_I32 : VOP3be_Real_ci <0x177>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VI // VI
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
▲ Show 20 Lines • Show All 100 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AMDGPU/vop3.s

Show First 20 Lines • Show All 380 Lines • ▼ Show 20 Lines
// SICI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0xd6,0x03] // SICI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0xd6,0x03]
// VI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0xd6,0x03] // VI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0xd6,0x03]
v_mad_f32 v9, 0.5, v5, -v8 v_mad_f32 v9, 0.5, v5, -v8
// SICI: v_mad_f32 v9, 0.5, v5, -v8 ; encoding: [0x09,0x00,0x82,0xd2,0xf0,0x0a,0x22,0x84] // SICI: v_mad_f32 v9, 0.5, v5, -v8 ; encoding: [0x09,0x00,0x82,0xd2,0xf0,0x0a,0x22,0x84]
// VI: v_mad_f32 v9, 0.5, v5, -v8 ; encoding: [0x09,0x00,0xc1,0xd1,0xf0,0x0a,0x22,0x84] // VI: v_mad_f32 v9, 0.5, v5, -v8 ; encoding: [0x09,0x00,0xc1,0xd1,0xf0,0x0a,0x22,0x84]
v_mqsad_u32_u8 v[0:3], s[2:3], v4, v[0:3] v_mqsad_u32_u8 v[0:3], s[2:3], v4, v[0:3]
// CI: v_mqsad_u32_u8 v[0:3], s[2:3], v4, v[0:3] ; encoding: [0x00,0x00,0xe8,0xd2,0x02,0x08,0x02,0x04] // CI: v_mqsad_u32_u8 v[0:3], s[2:3], v4, v[0:3] ; encoding: [0x00,0x00,0xea,0xd2,0x02,0x08,0x02,0x04]
// VI: v_mqsad_u32_u8 v[0:3], s[2:3], v4, v[0:3] ; encoding: [0x00,0x00,0xe7,0xd1,0x02,0x08,0x02,0x04] // VI: v_mqsad_u32_u8 v[0:3], s[2:3], v4, v[0:3] ; encoding: [0x00,0x00,0xe7,0xd1,0x02,0x08,0x02,0x04]
// NOSI: error: instruction not supported on this GPU // NOSI: error: instruction not supported on this GPU
v_mad_u64_u32 v[5:6], s[12:13], s1, 0, 0 v_mad_u64_u32 v[5:6], s[12:13], s1, 0, 0
// CI: v_mad_u64_u32 v[5:6], s[12:13], s1, 0, 0 ; encoding: [0x05,0x0c,0xec,0xd2,0x01,0x00,0x01,0x02] // CI: v_mad_u64_u32 v[5:6], s[12:13], s1, 0, 0 ; encoding: [0x05,0x0c,0xec,0xd2,0x01,0x00,0x01,0x02]
// VI: v_mad_u64_u32 v[5:6], s[12:13], s1, 0, 0 ; encoding: [0x05,0x0c,0xe8,0xd1,0x01,0x00,0x01,0x02] // VI: v_mad_u64_u32 v[5:6], s[12:13], s1, 0, 0 ; encoding: [0x05,0x0c,0xe8,0xd1,0x01,0x00,0x01,0x02]
// NOSI: error: instruction not supported on this GPU // NOSI: error: instruction not supported on this GPU
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