[mips] NaCl should now use the custom MipsELFStreamer (recently added) in spite of MCELFStreamer.

[matheusalmeida]

Summary

[mips] NaCl should now use the custom MipsELFStreamer (recently added) in spite of MCELFStreamer.
This is so that changes to MipsELFStreamer will automatically propagate through its subclasses.

No functional changes.

[dsanders]

LGTM but I think you should run it past Sasa before you commit

[sstankovic]

LGTM

[matheusalmeida]

Closed by commit rL204918 (authored by @matheusalmeida).

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h

 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
                                   bool *IsStore = NULL);
 bool baseRegNeedsLoadStoreMask(unsigned Reg);
 
 // This function creates an MCELFStreamer for Mips NaCl.
 MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context, MCAsmBackend &TAB,
                                          raw_ostream &OS,
                                          MCCodeEmitter *Emitter,
+                                         const MCSubtargetInfo &STI,
                                          bool RelaxAll, bool NoExecStack);
 
 }
 
 #endif

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
                                     raw_ostream &OS, MCCodeEmitter *Emitter,
                                     const MCSubtargetInfo &STI,
                                     bool RelaxAll, bool NoExecStack) {
   MCStreamer *S;
   if (!Triple(TT).isOSNaCl())
     S = createMipsELFStreamer(Context, MAB, OS, Emitter, STI, RelaxAll,
                               NoExecStack);
   else
-    S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll,
+    S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, STI, RelaxAll,
                                   NoExecStack);
   new MipsTargetELFStreamer(*S, STI);
   return S;
 }
 
 static MCStreamer *
 createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
                     bool isVerboseAsm, bool useCFI, bool useDwarfDirectory,

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp

 // emitted in the same bundle.  It aligns call + branch delay to the bundle end,
 // so that return address is always aligned to the start of next bundle.
 //
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "mips-mc-nacl"
 
 #include "Mips.h"
+#include "MipsELFStreamer.h"
 #include "MipsMCNaCl.h"
 #include "llvm/MC/MCELFStreamer.h"
 
 using namespace llvm;
 
 namespace {
 
 const unsigned IndirectBranchMaskReg = Mips::T6;
 const unsigned LoadStoreStackMaskReg = Mips::T7;
 
 /// Extend the generic MCELFStreamer class so that it can mask dangerous
 /// instructions.
 
-class MipsNaClELFStreamer : public MCELFStreamer {
+class MipsNaClELFStreamer : public MipsELFStreamer {
 public:
   MipsNaClELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS,
-                      MCCodeEmitter *Emitter)
-    : MCELFStreamer(Context, TAB, OS, Emitter), PendingCall(false) {}
+                      MCCodeEmitter *Emitter, const MCSubtargetInfo &STI)
+    : MipsELFStreamer(Context, TAB, OS, Emitter, STI), PendingCall(false) {}
 
   ~MipsNaClELFStreamer() {}
 
 private:
   // Whether we started the sandboxing sequence for calls.  Calls are bundled
   // with branch delays and aligned to the bundle end.
   bool PendingCall;
 
private:
 
   void emitMask(unsigned AddrReg, unsigned MaskReg,
                 const MCSubtargetInfo &STI) {
     MCInst MaskInst;
     MaskInst.setOpcode(Mips::AND);
     MaskInst.addOperand(MCOperand::CreateReg(AddrReg));
     MaskInst.addOperand(MCOperand::CreateReg(AddrReg));
     MaskInst.addOperand(MCOperand::CreateReg(MaskReg));
-    MCELFStreamer::EmitInstruction(MaskInst, STI);
+    MipsELFStreamer::EmitInstruction(MaskInst, STI);
   }
 
   // Sandbox indirect branch or return instruction by inserting mask operation
   // before it.
   void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) {
     unsigned AddrReg = MI.getOperand(0).getReg();
 
     EmitBundleLock(false);
     emitMask(AddrReg, IndirectBranchMaskReg, STI);
-    MCELFStreamer::EmitInstruction(MI, STI);
+    MipsELFStreamer::EmitInstruction(MI, STI);
     EmitBundleUnlock();
   }
 
   // Sandbox memory access or SP change.  Insert mask operation before and/or
   // after the instruction.
   void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx,
                                    const MCSubtargetInfo &STI, bool MaskBefore,
                                    bool MaskAfter) {
     EmitBundleLock(false);
     if (MaskBefore) {
       // Sandbox memory access.
       unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
       emitMask(BaseReg, LoadStoreStackMaskReg, STI);
     }
-    MCELFStreamer::EmitInstruction(MI, STI);
+    MipsELFStreamer::EmitInstruction(MI, STI);
     if (MaskAfter) {
       // Sandbox SP change.
       unsigned SPReg = MI.getOperand(0).getReg();
       assert((Mips::SP == SPReg) && "Unexpected stack-pointer register.");
       emitMask(SPReg, LoadStoreStackMaskReg, STI);
     }
     EmitBundleUnlock();
   }
if (IsMemAccess || IsSPFirstOperand) {
 
       bool MaskBefore = (IsMemAccess
                          && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx)
                                                           .getReg()));
       bool MaskAfter = IsSPFirstOperand && !IsStore;
       if (MaskBefore || MaskAfter)
         sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter);
       else
-        MCELFStreamer::EmitInstruction(Inst, STI);
+        MipsELFStreamer::EmitInstruction(Inst, STI);
       return;
     }
 
     // Sandbox calls by aligning call and branch delay to the bundle end.
     // For indirect calls, emit the mask before the call.
     bool IsIndirectCall;
     if (isCall(Inst.getOpcode(), &IsIndirectCall)) {
       if (PendingCall)
         report_fatal_error("Dangerous instruction in branch delay slot!");
 
       // Start the sandboxing sequence by emitting call.
       EmitBundleLock(true);
       if (IsIndirectCall) {
         unsigned TargetReg = Inst.getOperand(1).getReg();
         emitMask(TargetReg, IndirectBranchMaskReg, STI);
       }
-      MCELFStreamer::EmitInstruction(Inst, STI);
+      MipsELFStreamer::EmitInstruction(Inst, STI);
       PendingCall = true;
       return;
     }
     if (PendingCall) {
       // Finish the sandboxing sequence by emitting branch delay.
-      MCELFStreamer::EmitInstruction(Inst, STI);
+      MipsELFStreamer::EmitInstruction(Inst, STI);
       EmitBundleUnlock();
       PendingCall = false;
       return;
     }
 
     // None of the sandboxing applies, just emit the instruction.
-    MCELFStreamer::EmitInstruction(Inst, STI);
+    MipsELFStreamer::EmitInstruction(Inst, STI);
   }
 };
 
 } // end anonymous namespace
 
 namespace llvm {
 
 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,

 
 bool baseRegNeedsLoadStoreMask(unsigned Reg) {
   // The contents of SP and thread pointer register do not require masking.
   return Reg != Mips::SP && Reg != Mips::T8;
 }
 
 MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context, MCAsmBackend &TAB,
                                          raw_ostream &OS,
-                                         MCCodeEmitter *Emitter, bool RelaxAll,
-                                         bool NoExecStack) {
-  MipsNaClELFStreamer *S = new MipsNaClELFStreamer(Context, TAB, OS, Emitter);
+                                         MCCodeEmitter *Emitter,
+                                         const MCSubtargetInfo &STI,
+                                         bool RelaxAll, bool NoExecStack) {
+  MipsNaClELFStreamer *S = new MipsNaClELFStreamer(Context, TAB, OS, Emitter,
+                                                   STI);
   if (RelaxAll)
     S->getAssembler().setRelaxAll(true);
   if (NoExecStack)
     S->getAssembler().setNoExecStack(true);
 
   // Set bundle-alignment as required by the NaCl ABI for the target.
   S->EmitBundleAlignMode(MIPS_NACL_BUNDLE_ALIGN);
 
   return S;
 }
 
 }