[mips] Add MipsOptionRecord abstraction.

[tomatabacu]

Summary

This abstraction was created to help storing arbitrary information in ELF files.
For example, register usage can be stored in Mips specific ELF sections like .Mips.options.
Arbitrary records of .Mips.options should subclass MipsOptionRecord and provide
an implementation to EmitMipsOptionRecord.

The MipsELFStreamer class owns all the records and is responsible for their
creation and destruction.

[jacksprat]

Keeping in mind that I am drifting away from code and into retirement:

I am concerned that we have to loop through every potential register for each instruction register operand to determine use. Is there not a quicker way to do this? How does the codegen do it? Can it be done with a mask?

Does this routine get called for both direct object and asm?

Is this shared with .reginfo generation? I think so, but it wasn't obvious.

Jack

[matheusalmeida]

I am concerned that we have to loop through every potential register for each instruction register operand to determine use. Is there not a quicker way to do this? How does the codegen do it? Can it be done with a mask?

Not as far as I know. CodeGen uses the MachineRegisterInfo as the main abstraction to keep track of registers and afaik this is not accessible from the MC layer.

Does this routine get called for both direct object and asm?

Yes. For assembly input it's called from MipsAsmParser::MatchAndEmitInstruction and from direct object emission it's called from MipsAsmPrinter::EmitInstruction which calls EmitToStreamer which then calls the EmitInstruction in the ELF streamer.

Is this shared with .reginfo generation? I think so, but it wasn't obvious.

Yes. I wrote this comment that explains the logic of handling .Mips.options and .reginfo in the same function.

// We need to distinguish between N64 and the rest because at the moment
// we don't emit .Mips.options for other ELFs other than N64.
// Since .reginfo has the same information as .Mips.options (ODK_REGINFO),
// we can use the same abstraction (MipsRegInfo class) to handle both.

If it's not clear, please say so.

[matheusalmeida]

MipsELFStreamer now access MCInstrDesc from a global array defined in MipsGenInstrInfo.inc.
This is much better than accessing it via MipsMCCodeEmitter.

[dsanders]

All nits except for the MipsELFStreamer destructor

lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h

30–31

They can't be null so I'd make them references instead of pointers.

38–50

This should delete any MipsOptionRecord in MipsOptionRecords.

40

Add a doc comment describing the extra bit it does.

42–43

Drop the 'As the name suggests' and use '///' so it shows up in doxygen.

lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp

30

Is the T.isArch64Bit() necessary? I think testing for N64 is enough.

[matheusalmeida]

Addressing concerns.

The destructor in MipsELFStreamer now deletes all the stored MipsOptionRecord* in the vector. The vector is still a vector of pointers because it's not possible to have a vector of references.
Added doxygen style comments to the suggested functions.
Removed superfluous T.isArch64Bit() check.

[dsanders]

LGTM. Just one nit about the comments

lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h

45

I've had previous feedback asking me not to repeat the function name in the comment.

[tomatabacu]

Commandeered to finish off the patch and make it ready for commit.

[tomatabacu]

Rebased to trunk.

For MipsELFStreamer.h:
Reordered #include directives to conform with the recommended lexicographical order.
Renamed the EmitOptionRecords() to EmitMipsOptionRecords().

For MipsELFStreamer.cpp:
Removed anonymous namespace and made the getInstDesc function static instead.
Replaced call to Context.getRegisterInfo() with the appropriate local variable, MCRegInfo, when assigning to RegClassID.
Refactored for loop inside EmitMipsOptionRecords() to a range-based for loop.

For MipsTargetStreamer.cpp:
Replaced call to EmitOptionRecords() with EmitMipsOptionRecords().

[tomatabacu]

Fixed formatting for the SmallVector<MipsOptionRecord *, 8> type.

[matheusalmeida]

Hi Toma,

(Obviously) Feel free to commit. The reason I haven't done so (and I apologise!) was because I had some troubles convincing the dmz portal buildbots to pick up changes from my branch so that I could run the llvm test suite and then I forgot about this patch...

Regards,
Matheus

[dsanders]

Toma doesn't have commit access yet so I'll be committing for him for the first few patches.

The status of C++11 has moved on since I last reviewed this patch. It was quite new at the time but is now fairly well tested so I'd like to use unique_ptr to remove the need for explicit memory management of the new objects. This will also fix a memory leak I failed to spot. I'd also like to try the MCSubRegIterator technique mentioned in one of the FIXME comments to try and avoid the reference to MipsInsts if possible.

lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h

30–31

We should make both of these use unique_ptrs. This removes the need for a destructor and fixes the memory leak caused by forgetting to delete RegInfo.

49

Blank line needed above comment. As mentioned earlier in the review, I've been asked not to repeat the function name in the comment.

lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp

67–68

We should definitely try to do this before we commit this patch. It should be a fairly easy change and removes the need to test register class membership which in turn removes the need to reference the internals of the tablegen-erated code.

[tomatabacu]

MipsELFStreamer.h:
Converted existing raw pointers to the shared_ptr type.
Removed destructor.
Fixed blank line and function names in comments.
Removed unused header:

#include "llvm/Support/raw_ostream.h"

Added header for smart pointers:

#include <memory>

MipsELFStreamer.cpp:
Renamed NumOp to OpIndex, for clarity.
Moved the RegClass related code from EmitInstruction to the MipsRegInfoRecord class.
Removed declaration of MipsInsts[].
Removed definition of getInstDesc.
Removed the following unused headers:

#include "MipsMCTargetDesc.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/ELF.h"

MipsOptionRecord.h:
Renamed MipsRegInfo to MipsRegInfoRecord.
Changed the arguments for SetPhysRegUsed().
Added private members of MCRegisterClass type which are used when checking if a given
register belongs to a class in SetPhysRegUsed.
Replaced ri_gp_value64 and ri_gp_value32 with a single 64-bit ri_gp_value.
Removed the following unused headers:

#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/DataTypes.h"

Added the following headers:

#include "MipsMCTargetDesc.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCRegisterInfo.h"

Removed the following unnecessary forward declarations:

class MCContext;
class MCELFStreamer;
class MCStreamer;

MipsOptionRecord.cpp:
In MipsRegInfoRecord::EmitMipsOptionRecord, changed code to use a single ri_gp_value.
MipsRegInfoRecord::SetPhysRegUsed is now using MCSubRegIterator to set the mask correctly.
MipsRegInfoRecord::SetPhysRegUsed is no longer checking RegClassIDs and instead uses the
MCRegisterClass private members.
Removed the following unused headers:

#include "MipsMCTargetDesc.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCStreamer.h"

[dsanders]

This is nearly ready to commit. You just need to reduce the MSA register set membership tests to (any) one of the MSA register classes, undo the two incidental comment changes (the changes aren't wrong, they just belong in another patch), and add the missing newline at EOF.

One other thing to mention is that you're going a bit too far with the detail in your updates at the moment. You need to describe what you changed (e.g. algorithm or general approach) and why but you don't need to describe the mechanical changes used to accomplish it.
For example, I would describe your latest update like this:

Removed the need to access internals of the tablegen-erated code (MipsInsts)
to determine register usage. The new implementation uses MCSubRegIterator instead.

Use shared_ptr for .MIPS.option records. unique_ptr cannot be used since the
pointer is shared between MipsOptionRecords and RegInfoRecord.

Renamed MipsELFStreamer::RegInfo and MipsRegInfo class to avoid confusion with
TargetRegisterInfo and other uses of the term 'RegInfo'.

Merge ri_gp_value32 and ri_gp_value64 into a single variable (ri_gp_value) and check
for overflow when writing the 32-bit case

Unfortunately, it's rather difficult to write guidelines for what needs mentioning and what you can have the patch say for itself. You'll gradually get a feel for the level of detail that's needed.

lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h

44

Try to avoid making incidental changes in the same patch since they can make the patch noisy and difficult to review. This should be a separate cleanup patch if we decide to do it. For comments that repeat the function name like this, we generally leave the existing cases until we need to change the comment or the related function.

50

Another incidental change.

lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp

79–82

It's not necessary to test all four of these MSA classes since they all contain the same registers. We only need to test one (it doesn't matter which).

93

Missing newline at EOF

lib/Target/Mips/MipsOptionRecord.h

56–59

As above, we only need one of these.

[dsanders]

lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h

44

My apologies. This isn't an incidental change, I was looking at the diff-between-diffs view.

50

This one isn't incidental either. Sorry for the noise.

[tomatabacu]

Addressed concerns and reflowed comments in MipsELFStreamer.h.
Rebased to trunk (also integrated alignment setting for ".MIPS.options" and ".reginfo").
Fixed tests broken by rebase.

[tomatabacu]

Changed shared_ptr members to uniqe_ptr vector and raw pointer variable.

Fixed abiflags.s tests to not have strict checks on the section header string table
offset.

Fix alignment for .reginfo (because of rebase).

Rebased to trunk.

[tomatabacu]

Fixed formatting.

[dsanders]

LGTM. Committed in r213522

lib/Target/Mips/MCTargetDesc/CMakeLists.txt

 add_llvm_library(LLVMMipsDesc
   MipsABIFlagsSection.cpp
   MipsAsmBackend.cpp
   MipsELFObjectWriter.cpp
   MipsELFStreamer.cpp
   MipsMCAsmInfo.cpp
   MipsMCCodeEmitter.cpp
   MipsMCExpr.cpp
   MipsMCTargetDesc.cpp
   MipsNaClELFStreamer.cpp
+  MipsOptionRecord.cpp
   MipsTargetStreamer.cpp
   )

lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h

 // This is a custom MCELFStreamer which allows us to insert some hooks before
 // emitting data into an actual object file.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MIPSELFSTREAMER_H
 #define MIPSELFSTREAMER_H
 
+#include "MipsOptionRecord.h"
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCELFStreamer.h"
-#include "llvm/Support/raw_ostream.h"
+#include <memory>
 
 namespace llvm {
 class MCAsmBackend;
 class MCCodeEmitter;
 class MCContext;
 class MCSubtargetInfo;
 
 class MipsELFStreamer : public MCELFStreamer {
+  SmallVector<std::unique_ptr<MipsOptionRecord>, 8> MipsOptionRecords;
+  MipsRegInfoRecord *RegInfoRecord;
 
 public:
   MipsELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS,
                   MCCodeEmitter *Emitter, const MCSubtargetInfo &STI)
-      : MCELFStreamer(Context, MAB, OS, Emitter) {}
+      : MCELFStreamer(Context, MAB, OS, Emitter) {
 
-  virtual ~MipsELFStreamer() {}
+    RegInfoRecord = new MipsRegInfoRecord(this, Context, STI);
+    MipsOptionRecords.push_back(
+        std::unique_ptr<MipsRegInfoRecord>(RegInfoRecord));
+  }
+
+  /// Overriding this function allows us to add arbitrary behaviour before the
+  /// \p Inst is actually emitted. For example, we can inspect the operands and
+  /// gather sufficient information that allows us to reason about the register
+  /// usage for the translation unit.
+  void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
+
+  /// Emits all the option records stored up until the point it's called.
+  void EmitMipsOptionRecords();
 };
 
 MCELFStreamer *createMipsELFStreamer(MCContext &Context, MCAsmBackend &MAB,
                                      raw_ostream &OS, MCCodeEmitter *Emitter,
                                      const MCSubtargetInfo &STI, bool RelaxAll,
                                      bool NoExecStack);
 } // namespace llvm.
 #endif

lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp

 //===-------- MipsELFStreamer.cpp - ELF Object Output ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MipsELFStreamer.h"
+#include "llvm/MC/MCInst.h"
+
+void MipsELFStreamer::EmitInstruction(const MCInst &Inst,
+                                      const MCSubtargetInfo &STI) {
+  MCELFStreamer::EmitInstruction(Inst, STI);
+
+  MCContext &Context = getContext();
+  const MCRegisterInfo *MCRegInfo = Context.getRegisterInfo();
+
+  for (unsigned OpIndex = 0; OpIndex < Inst.getNumOperands(); ++OpIndex) {
+    const MCOperand &Op = Inst.getOperand(OpIndex);
+
+    if (!Op.isReg())
+      continue;
+
+    unsigned Reg = Op.getReg();
+    RegInfoRecord->SetPhysRegUsed(Reg, MCRegInfo);
+  }
+}
+
+void MipsELFStreamer::EmitMipsOptionRecords() {
+  for (const auto &I : MipsOptionRecords)
+    I->EmitMipsOptionRecord();
+}
 
 namespace llvm {
 MCELFStreamer *createMipsELFStreamer(MCContext &Context, MCAsmBackend &MAB,
                                      raw_ostream &OS, MCCodeEmitter *Emitter,
                                      const MCSubtargetInfo &STI, bool RelaxAll,
                                      bool NoExecStack) {
   return new MipsELFStreamer(Context, MAB, OS, Emitter, STI);
 }
 }

lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp

+//===-- MipsOptionRecord.cpp - Abstraction for storing information --------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "MipsOptionRecord.h"
+#include "MipsELFStreamer.h"
+#include "llvm/MC/MCSectionELF.h"
+
+using namespace llvm;
+
+void MipsRegInfoRecord::EmitMipsOptionRecord() {
+  MCAssembler &MCA = Streamer->getAssembler();
+  Triple T(STI.getTargetTriple());
+  uint64_t Features = STI.getFeatureBits();
+
+  Streamer->PushSection();
+
+  // We need to distinguish between N64 and the rest because at the moment
+  // we don't emit .Mips.options for other ELFs other than N64.
+  // Since .reginfo has the same information as .Mips.options (ODK_REGINFO),
+  // we can use the same abstraction (MipsRegInfoRecord class) to handle both.
+  if (Features & Mips::FeatureN64) {
+    // The EntrySize value of 1 seems strange since the records are neither
+    // 1-byte long nor fixed length but it matches the value GAS emits.
+    const MCSectionELF *Sec =
+        Context.getELFSection(".MIPS.options", ELF::SHT_MIPS_OPTIONS,
+                              ELF::SHF_ALLOC | ELF::SHF_MIPS_NOSTRIP,
+                              SectionKind::getMetadata(), 1, "");
+    MCA.getOrCreateSectionData(*Sec).setAlignment(8);
+    Streamer->SwitchSection(Sec);
+
+    Streamer->EmitIntValue(1, 1);  // kind
+    Streamer->EmitIntValue(40, 1); // size
+    Streamer->EmitIntValue(0, 2);  // section
+    Streamer->EmitIntValue(0, 4);  // info
+    Streamer->EmitIntValue(ri_gprmask, 4);
+    Streamer->EmitIntValue(0, 4); // pad
+    Streamer->EmitIntValue(ri_cprmask[0], 4);
+    Streamer->EmitIntValue(ri_cprmask[1], 4);
+    Streamer->EmitIntValue(ri_cprmask[2], 4);
+    Streamer->EmitIntValue(ri_cprmask[3], 4);
+    Streamer->EmitIntValue(ri_gp_value, 8);
+  } else {
+    const MCSectionELF *Sec =
+        Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO, ELF::SHF_ALLOC,
+                              SectionKind::getMetadata(), 24, "");
+    MCA.getOrCreateSectionData(*Sec)
+        .setAlignment(Features & Mips::FeatureN32 ? 8 : 4);
+    Streamer->SwitchSection(Sec);
+
+    Streamer->EmitIntValue(ri_gprmask, 4);
+    Streamer->EmitIntValue(ri_cprmask[0], 4);
+    Streamer->EmitIntValue(ri_cprmask[1], 4);
+    Streamer->EmitIntValue(ri_cprmask[2], 4);
+    Streamer->EmitIntValue(ri_cprmask[3], 4);
+    assert((ri_gp_value & 0xffffffff) == ri_gp_value);
+    Streamer->EmitIntValue(ri_gp_value, 4);
+  }
+
+  Streamer->PopSection();
+}
+
+void MipsRegInfoRecord::SetPhysRegUsed(unsigned Reg,
+                                       const MCRegisterInfo *MCRegInfo) {
+  unsigned Value = 0;
+
+  for (MCSubRegIterator SubRegIt(Reg, MCRegInfo, true); SubRegIt.isValid();
+       ++SubRegIt) {
+    unsigned CurrentSubReg = *SubRegIt;
+
+    unsigned EncVal = MCRegInfo->getEncodingValue(CurrentSubReg);
+    Value |= 1 << EncVal;
+
+    if (GPR32RegClass->contains(CurrentSubReg) ||
+        GPR64RegClass->contains(CurrentSubReg))
+      ri_gprmask |= Value;
+    else if (FGR32RegClass->contains(CurrentSubReg) ||
+             FGR64RegClass->contains(CurrentSubReg) ||
+             AFGR64RegClass->contains(CurrentSubReg) ||
+             MSA128BRegClass->contains(CurrentSubReg))
+      ri_cprmask[1] |= Value;
+    else if (COP2RegClass->contains(CurrentSubReg))
+      ri_cprmask[2] |= Value;
+    else if (COP3RegClass->contains(CurrentSubReg))
+      ri_cprmask[3] |= Value;
+  }
+}

lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides Mips specific target streamer methods.
 //
 //===----------------------------------------------------------------------===//
 
 #include "InstPrinter/MipsInstPrinter.h"
+#include "MipsELFStreamer.h"
 #include "MipsMCTargetDesc.h"
 #include "MipsTargetObjectFile.h"
 #include "MipsTargetStreamer.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCELF.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbol.h"
void MipsTargetELFStreamer::emitLabel(MCSymbol *Symbol) {
   // The "other" values are stored in the last 6 bits of the second byte
   // The traditional defines for STO values assume the full byte and thus
   // the shift to pack it.
   MCELF::setOther(Data, ELF::STO_MIPS_MICROMIPS >> 2);
 }
 
 void MipsTargetELFStreamer::finish() {
   MCAssembler &MCA = getStreamer().getAssembler();
-  MCContext &Context = MCA.getContext();
-  MCStreamer &OS = getStreamer();
-  const MCObjectFileInfo &OFI = *Context.getObjectFileInfo();
-  Triple T(STI.getTargetTriple());
-  uint64_t Features = STI.getFeatureBits();
+  const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
 
   // .bss, .text and .data are always at least 16-byte aligned.
   MCSectionData &TextSectionData =
       MCA.getOrCreateSectionData(*OFI.getTextSection());
   MCSectionData &DataSectionData =
       MCA.getOrCreateSectionData(*OFI.getDataSection());
   MCSectionData &BSSSectionData =
       MCA.getOrCreateSectionData(*OFI.getBSSSection());
 
   TextSectionData.setAlignment(std::max(16u, TextSectionData.getAlignment()));
   DataSectionData.setAlignment(std::max(16u, DataSectionData.getAlignment()));
   BSSSectionData.setAlignment(std::max(16u, BSSSectionData.getAlignment()));
 
-  if (T.isArch64Bit() && (Features & Mips::FeatureN64)) {
-    // The EntrySize value of 1 seems strange since the records are neither
-    // 1-byte long nor fixed length but it matches the value GAS emits.
-    const MCSectionELF *Sec =
-        Context.getELFSection(".MIPS.options", ELF::SHT_MIPS_OPTIONS,
-                              ELF::SHF_ALLOC | ELF::SHF_MIPS_NOSTRIP,
-                              SectionKind::getMetadata(), 1, "");
-    MCA.getOrCreateSectionData(*Sec).setAlignment(8);
-    OS.SwitchSection(Sec);
+  // Emit all the option records.
+  // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
+  // .reginfo.
+  MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
+  MEF.EmitMipsOptionRecords();
 
-    OS.EmitIntValue(1, 1);  // kind
-    OS.EmitIntValue(40, 1); // size
-    OS.EmitIntValue(0, 2);  // section
-    OS.EmitIntValue(0, 4);  // info
-    OS.EmitIntValue(0, 4);  // ri_gprmask
-    OS.EmitIntValue(0, 4);  // pad
-    OS.EmitIntValue(0, 4);  // ri_cpr[0]mask
-    OS.EmitIntValue(0, 4);  // ri_cpr[1]mask
-    OS.EmitIntValue(0, 4);  // ri_cpr[2]mask
-    OS.EmitIntValue(0, 4);  // ri_cpr[3]mask
-    OS.EmitIntValue(0, 8);  // ri_gp_value
-  } else {
-    const MCSectionELF *Sec =
-        Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO, ELF::SHF_ALLOC,
-                              SectionKind::getMetadata(), 24, "");
-    MCA.getOrCreateSectionData(*Sec)
-        .setAlignment(Features & Mips::FeatureN32 ? 8 : 4);
-    OS.SwitchSection(Sec);
-
-    OS.EmitIntValue(0, 4); // ri_gprmask
-    OS.EmitIntValue(0, 4); // ri_cpr[0]mask
-    OS.EmitIntValue(0, 4); // ri_cpr[1]mask
-    OS.EmitIntValue(0, 4); // ri_cpr[2]mask
-    OS.EmitIntValue(0, 4); // ri_cpr[3]mask
-    OS.EmitIntValue(0, 4); // ri_gp_value
-  }
   emitMipsAbiFlags();
 }
 
 void MipsTargetELFStreamer::emitAssignment(MCSymbol *Symbol,
                                            const MCExpr *Value) {
   // If on rhs is micromips symbol then mark Symbol as microMips.
   if (Value->getKind() != MCExpr::SymbolRef)
     return;

lib/Target/Mips/MipsOptionRecord.h

+//===-- MipsOptionRecord.h - Abstraction for storing information ----------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// MipsOptionRecord - Abstraction for storing arbitrary information in
+// ELF files. Arbitrary information (e.g. register usage) can be stored in Mips
+// specific ELF sections like .Mips.options. Specific records should subclass
+// MipsOptionRecord and provide an implementation to EmitMipsOptionRecord which
+// basically just dumps the information into an ELF section. More information
+// about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
+// specification.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MIPSOPTIONRECORD_H
+#define MIPSOPTIONRECORD_H
+
+#include "MipsMCTargetDesc.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCRegisterInfo.h"
+
+using namespace llvm;
+
+namespace llvm {
+class MipsELFStreamer;
+class MCSubtargetInfo;
+}
+
+class MipsOptionRecord {
+public:
+  virtual ~MipsOptionRecord(){};
+  virtual void EmitMipsOptionRecord() = 0;
+};
+
+class MipsRegInfoRecord : public MipsOptionRecord {
+public:
+  MipsRegInfoRecord(MipsELFStreamer *S, MCContext &Context,
+                    const MCSubtargetInfo &STI)
+      : Streamer(S), Context(Context), STI(STI) {
+    ri_gprmask = 0;
+    ri_cprmask[0] = ri_cprmask[1] = ri_cprmask[2] = ri_cprmask[3] = 0;
+    ri_gp_value = 0;
+
+    const MCRegisterInfo *TRI = Context.getRegisterInfo();
+    GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
+    GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
+    FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
+    FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
+    AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
+    MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
+    COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
+    COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
+  }
+  ~MipsRegInfoRecord() {}
+
+  void EmitMipsOptionRecord();
+  void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo);
+
+private:
+  MipsELFStreamer *Streamer;
+  MCContext &Context;
+  const MCSubtargetInfo &STI;
+  const MCRegisterClass *GPR32RegClass;
+  const MCRegisterClass *GPR64RegClass;
+  const MCRegisterClass *FGR32RegClass;
+  const MCRegisterClass *FGR64RegClass;
+  const MCRegisterClass *AFGR64RegClass;
+  const MCRegisterClass *MSA128BRegClass;
+  const MCRegisterClass *COP2RegClass;
+  const MCRegisterClass *COP3RegClass;
+  uint32_t ri_gprmask;
+  uint32_t ri_cprmask[4];
+  int64_t ri_gp_value;
+};
+#endif

test/MC/Mips/mips-reginfo-fp32.s

+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o - | \
+# RUN:   llvm-readobj -s -section-data | \
+# RUN:     FileCheck %s
+
+# CHECK:   Section {
+# CHECK:    Index:
+# CHECK:    Name: .reginfo
+# CHECK:    Type: SHT_MIPS_REGINFO (0x70000006)
+# CHECK:    Flags [ (0x2)
+# CHECK:      SHF_ALLOC (0x2)
+# CHECK:    ]
+# CHECK:    Size: 24
+# CHECK:    SectionData (
+# CHECK:      0000: 01010101 00000000 C0007535 00000000
+# CHECK:      0010: 00000000 00000000
+# CHECK:    )
+# CHECK:  }
+
+.text
+        add $0,$0,$0
+        add $8,$0,$0
+        add $16,$0,$0
+        add $24,$0,$0
+
+# abs.s - Reads and writes from/to $f0.
+        abs.s $f0,$f0
+# round.w.d - Reads $f4 and $f5 and writes to $f2.
+        round.w.d $f2,$f4
+# ceil.w.s - Reads $f8 and writes to $f10.
+        ceil.w.s $f10, $f8
+# cvt.s.d - Reads from $f12 and $f13 and writes to $f14
+        cvt.s.d $f14, $f12
+# abs.d - Reads from $f30 and $f31 and writes to $f30 and $f31.
+        abs.d $f30,$f30

test/MC/Mips/mips-reginfo-fp64.s

+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa,+fp64 -filetype=obj -o - | \
+# RUN:   llvm-readobj -s -section-data | \
+# RUN:     FileCheck %s -check-prefix=ELF32
+
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64,-n64,+n32 -filetype=obj -o - | \
+# RUN:   llvm-readobj -s -section-data | \
+# RUN:     FileCheck %s -check-prefix=ELF32
+
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64,+n64 -filetype=obj -o - | \
+# RUN:   llvm-readobj -s -section-data | \
+# RUN:     FileCheck %s -check-prefix=ELF64
+
+# ELF32:   Section {
+# ELF32:    Name: .reginfo
+# ELF32:    Type: SHT_MIPS_REGINFO (0x70000006)
+# ELF32:    Flags [ (0x2)
+# ELF32:      SHF_ALLOC (0x2)
+# ELF32:    ]
+# ELF32:    Size: 24
+# ELF32:    SectionData (
+# ELF32:      0000: 01010101 00000000 4C005515 00000000
+# ELF32:      0010: 00000000 00000000
+# ELF32:    )
+# ELF32:  }
+
+# ELF64:   Section {
+# ELF64:    Name: .MIPS.options
+# ELF64:    Type: SHT_MIPS_OPTIONS (0x7000000D)
+# ELF64:    Flags [ (0x8000002)
+# ELF64:      SHF_ALLOC (0x2)
+# ELF64:      SHF_MIPS_NOSTRIP (0x8000000)
+# ELF64:    ]
+# ELF64:    Size: 40
+# ELF64:    SectionData (
+# ELF64:      0000: 01280000 00000000 01010101 00000000
+# ELF64:      0010: 00000000 4C005515 00000000 00000000
+# ELF64:      0020: 00000000 00000000
+# ELF64:    )
+# ELF64:  }
+
+.text
+        add $0,$0,$0
+        add $8,$0,$0
+        add $16,$0,$0
+        add $24,$0,$0
+
+# abs.s - Reads and writes from/to $f0.
+        abs.s $f0,$f0
+# round.w.d - Reads $f4 and writes to $f2.
+        round.w.d $f2,$f4
+# ceil.w.s - Reads $f8 and writes to $f10.
+        ceil.w.s $f10, $f8
+# cvt.s.d - Reads from $f12 and writes to $f14.
+        cvt.s.d $f14, $f12
+# abs.d - Reads from $f30 and writes to $f30.
+        abs.d $f30,$f30
+
+# Read and write from/to $f26 and $f27
+        add_a.b $w26,$w26,$w26
+        add_a.b $w27,$w27,$w27

test/MC/Mips/mips64/abiflags.s

 # RUN: llvm-mc %s -arch=mips -mcpu=mips64 | \
 # RUN:   FileCheck %s -check-prefix=CHECK-ASM
 #
 # RUN: llvm-mc %s -arch=mips -mcpu=mips64 -filetype=obj -o - | \
 # RUN:   llvm-readobj -sections -section-data -section-relocations - | \
 # RUN:     FileCheck %s -check-prefix=CHECK-OBJ
 
 # CHECK-ASM: .module fp=64
 
 # Checking if the Mips.abiflags were correctly emitted.
 # CHECK-OBJ:       Section {
 # CHECK-OBJ:         Index: 5
-# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags (12)
+# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags
 # CHECK-OBJ:         Type: SHT_MIPS_ABIFLAGS (0x7000002A)
 # CHECK-OBJ:          Flags [ (0x2)
 # CHECK-OBJ:           SHF_ALLOC (0x2)
 # CHECK-OBJ:         ]
 # CHECK-OBJ:         Address: 0x0
 # CHECK-OBJ:         Size: 24
 # CHECK-OBJ:         Link: 0
 # CHECK-OBJ:         Info: 0

test/MC/Mips/mips64r2/abiflags.s

 # RUN: llvm-mc %s -arch=mips -mcpu=mips64r2 | \
 # RUN:   FileCheck %s -check-prefix=CHECK-ASM
 #
 # RUN: llvm-mc %s -arch=mips -mcpu=mips64r2 -filetype=obj -o - | \
 # RUN:   llvm-readobj -sections -section-data -section-relocations - | \
 # RUN:     FileCheck %s -check-prefix=CHECK-OBJ
 
 # CHECK-ASM: .module fp=64
 
 # Checking if the Mips.abiflags were correctly emitted.
 # CHECK-OBJ:       Section {
 # CHECK-OBJ:         Index: 5
-# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags (12)
+# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags
 # CHECK-OBJ:         Type: SHT_MIPS_ABIFLAGS (0x7000002A)
 # CHECK-OBJ:          Flags [ (0x2)
 # CHECK-OBJ:           SHF_ALLOC (0x2)
 # CHECK-OBJ:         ]
 # CHECK-OBJ:         Address: 0x0
 # CHECK-OBJ:         Size: 24
 # CHECK-OBJ:         Link: 0
 # CHECK-OBJ:         Info: 0