Improve DAGTypeLegalizer::PromoteIntRes_TRUNCATE() to handle widening.

[jonpa]

Summary

DAGTypeLegalizer::PromoteIntRes_TRUNCATE() did previously not handle the case where the operand needs to be widened, which resultet in a llvm_unreachable()l.

This was discovered with llvm-stress and reported at https://bugs.llvm.org/show_bug.cgi?id=32275. The stress test case is included also in this patch as a regression test for SystemZ.

The test case involves a truncate from v4i8 to v4i1. On SystemZ, v4i8 should be widened to v16i8.

t17: v16i8,ch = CopyFromReg t0, Register:v16i8 %vreg13
  t18: v4i8 = extract_subvector t17, Constant:i32<0>
     t19: v4i1 = truncate t18

The patch net result is (after type legalization)

                 t264: i32 = extract_vector_elt t17, Constant:i32<0>
                  t260: i32 = extract_vector_elt t17, Constant:i32<1>
                  t256: i32 = extract_vector_elt t17, Constant:i32<2>
                  t252: i32 = extract_vector_elt t17, Constant:i32<3>
           t222: v4i32 = BUILD_VECTOR t264, t260, t256, t252
      t112: v4i32 = BUILD_VECTOR Constant:i32<1>, Constant:i32<1>, Constant:i32<1>, Constant:i32<1>
  t224: v4i32 = and t222, t112
t270: v4i32 = sign_extend_inreg t224, ValueType:ch:v4i1

The final output does not look optimal, but since this is so rare, it should not matter.

[RKSimon]

test/CodeGen/SystemZ/vec-trunc-to-i1.ll

4

Reduced with bugpoint:

define void @autogen_SD29574() {
BB:
  %B15 = sub <4 x i8> undef, zeroinitializer
  br label %CF34

CF34:                                             ; preds = %CF34, %BB
  %Tr24 = trunc <4 x i8> %B15 to <4 x i1>
  %Cmp26 = icmp slt <4 x i1> %Tr24, undef
  %E28 = extractelement <4 x i1> %Cmp26, i32 3
  br i1 %E28, label %CF34, label %CF36

CF36:                                             ; preds = %CF34
  ret void
}

[jonpa]

Test case reduced. Thanks Simon.

test/CodeGen/SystemZ/vec-trunc-to-i1.ll

4

Oops - thought I had done that... thanks.

[RKSimon]

test/CodeGen/SystemZ/vec-trunc-to-i1.ll

4

You might be able to manually reduce it further. Also, you should probably rename the test pr32275 or something to indicate its origin.

[efriedma]

Code changes look fine; testcase could be better.

[jonpa]

Thanks for review.

I changed the name in the test case per Simons suggestion.

I tried also making this even smaller, but found that the problem didn't trigger if I removed the control flow, and my guess is that the DAG optimizations then hide this problem since it's now all just one DAG.

Is this test acceptable, or if not, what is the problem?

[efriedma]

I don't like tests which have constant-foldable operation involving undef; you might get lucky and it won't get folded right now, but that could very easily change in the future; then you aren't testing anything useful anymore. In this case, you can reduce the testcase to something like this:

define void @pr32275(<4 x i8> %B15) {
BB:
  br label %CF34

CF34:
  %Tr24 = trunc <4 x i8> %B15 to <4 x i1>
  %E28 = extractelement <4 x i1> %Tr24, i32 3
  br i1 %E28, label %CF34, label %CF36

CF36:
  ret void
}

Also, the CHECK lines should check that the test is actually generating some reasonable sequence, as opposed to just checking that it doesn't crash; that verifies the test is actually testing something relevant.

[jonpa]

In this case, you can reduce the testcase to something like this:

Test updated. CHECK lines generated with update_llc_test_checks.py.

[RKSimon]

LGTM

[jonpa]

Thanks for review, commited as r298357.

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
   default: llvm_unreachable("Unknown type action!");
   case TargetLowering::TypeLegal:
   case TargetLowering::TypeExpandInteger:
     Res = InOp;
     break;
   case TargetLowering::TypePromoteInteger:
     Res = GetPromotedInteger(InOp);
     break;
-  case TargetLowering::TypeSplitVector:
+  case TargetLowering::TypeSplitVector: {
     EVT InVT = InOp.getValueType();
     assert(InVT.isVector() && "Cannot split scalar types");
     unsigned NumElts = InVT.getVectorNumElements();
     assert(NumElts == NVT.getVectorNumElements() &&
            "Dst and Src must have the same number of elements");
     assert(isPowerOf2_32(NumElts) &&
            "Promoted vector type must be a power of two");
 
     SDValue EOp1, EOp2;
     GetSplitVector(InOp, EOp1, EOp2);
 
     EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
                                    NumElts/2);
     EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
     EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
 
     return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
   }
+  case TargetLowering::TypeWidenVector: {
+    SDValue WideInOp = GetWidenedVector(InOp);
+
+    // Truncate widened InOp.
+    unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
+    EVT TruncVT = EVT::getVectorVT(*DAG.getContext(),
+                                   N->getValueType(0).getScalarType(), NumElem);
+    SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp);
+
+    // Zero extend so that the elements are of same type as those of NVT
+    EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), NVT.getVectorElementType(),
+                                 NumElem);
+    SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc);
+
+    // Extract the low NVT subvector.
+    MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
+    SDValue ZeroIdx = DAG.getConstant(0, dl, IdxTy);
+    return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx);
+  }
+  }
 
   // Truncate to NVT instead of VT
   return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
   if (ResNo == 1)
     return PromoteIntRes_Overflow(N);

test/CodeGen/SystemZ/vec-trunc-to-i1.ll

+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+;
+; Check that a widening truncate to a vector of i1 elements can be handled.
+
+define void @autogen_SD29574(i8*, i32*, i64*, i32, i64, i8) {
+; CHECK: .text
+BB:
+  %A4 = alloca <8 x i32>
+  %A3 = alloca <16 x i64>
+  %A2 = alloca <2 x i16>
+  %A1 = alloca <16 x i32>
+  %A = alloca <4 x i32>
+  %L = load i8, i8* %0
+  store <16 x i32> zeroinitializer, <16 x i32>* %A1
+  %E = extractelement <4 x i16> zeroinitializer, i32 0
+  %Shuff = shufflevector <2 x i64> zeroinitializer, <2 x i64> zeroinitializer, <2 x i32> <i32 3, i32 1>
+  %I = insertelement <2 x i64> %Shuff, i64 111415, i32 1
+  %Tr = trunc <16 x i32> zeroinitializer to <16 x i16>
+  %Sl = select i1 true, float 0x469BEFFFC0000000, float 0x3952E376C0000000
+  %Cmp = fcmp une double 0xDB116CB0010F082E, 0x438536246B8353A2
+  br label %CF
+
+CF:                                               ; preds = %CF, %CF35, %BB
+  %L5 = load i8, i8* %0
+  store i32 0, i32* %1
+  %E6 = extractelement <8 x i16> zeroinitializer, i32 4
+  %Shuff7 = shufflevector <1 x i16> zeroinitializer, <1 x i16> zeroinitializer, <1 x i32> <i32 1>
+  %I8 = insertelement <2 x i64> zeroinitializer, i64 %4, i32 1
+  %B = shl i16 %E6, -1
+  %FC = fptoui float 0x3952E376C0000000 to i1
+  br i1 %FC, label %CF, label %CF35
+
+CF35:                                             ; preds = %CF
+  %Sl9 = select i1 true, <16 x i64>* %A3, <16 x i64>* %A3
+  %Cmp10 = icmp ult <2 x i64> %Shuff, %Shuff
+  %L11 = load <16 x i64>, <16 x i64>* %Sl9
+  store <16 x i64> %L11, <16 x i64>* %Sl9
+  %E12 = extractelement <2 x i8> zeroinitializer, i32 1
+  %Shuff13 = shufflevector <4 x i8> zeroinitializer, <4 x i8> zeroinitializer, <4 x i32> <i32 undef, i32 2, i32 4, i32 undef>
+  %I14 = insertelement <4 x i8> %Shuff13, i8 -1, i32 2
+  %B15 = sub <4 x i8> %I14, zeroinitializer
+  %Tr16 = trunc <4 x i8> %I14 to <4 x i1>
+  %Sl17 = select i1 true, i32 %3, i32 0
+  %Cmp18 = icmp sgt <2 x i64> %I, %Shuff
+  %L19 = load <16 x i64>, <16 x i64>* %Sl9
+  store <16 x i64> %L11, <16 x i64>* %Sl9
+  %E20 = extractelement <2 x i1> %Cmp18, i32 0
+  br i1 %E20, label %CF, label %CF34
+
+CF34:                                             ; preds = %CF34, %CF35
+  %Shuff21 = shufflevector <8 x i16> zeroinitializer, <8 x i16> zeroinitializer, <8 x i32> <i32 9, i32 11, i32 13, i32 15, i32 1, i32 undef, i32 undef, i32 7>
+  %I22 = insertelement <4 x i16> zeroinitializer, i16 %E6, i32 3
+  %B23 = srem i32 %Sl17, -1
+  %Tr24 = trunc <4 x i8> %B15 to <4 x i1>
+  %Sl25 = select i1 true, i16 -20525, i16 -20525
+  %Cmp26 = icmp slt <4 x i1> %Tr24, %Tr16
+  %L27 = load <16 x i64>, <16 x i64>* %Sl9
+  store <16 x i64> %L11, <16 x i64>* %Sl9
+  %E28 = extractelement <4 x i1> %Cmp26, i32 3
+  br i1 %E28, label %CF34, label %CF36
+
+CF36:                                             ; preds = %CF34
+  %Shuff29 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %Shuff21, <8 x i32> <i32 2, i32 undef, i32 6, i32 8, i32 undef, i32 12, i32 14, i32 undef>
+  %I30 = insertelement <4 x i1> %Tr24, i1 true, i32 0
+  %B31 = mul i32 0, 0
+  %Se = sext <4 x i1> %Tr16 to <4 x i8>
+  %Sl32 = select i1 true, i32 244675, i32 %Sl17
+  %Cmp33 = icmp ne <4 x i8> %Se, %Shuff13
+  store <16 x i64> %L11, <16 x i64>* %Sl9
+  store <16 x i64> %L11, <16 x i64>* %Sl9
+  store <16 x i64> %L11, <16 x i64>* %Sl9
+  store <16 x i64> %L11, <16 x i64>* %Sl9
+  store <16 x i64> %L11, <16 x i64>* %Sl9
+  ret void
+}