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Differential D30692

[ARM] Correct handling of LSL #0 in an IT block
ClosedPublic

Authored by john.brawn on Mar 7 2017, 6:32 AM.

Details

Reviewers
rengolin
jmolloy
olista01
Commits
rGeba9fdac7e13: [ARM] Correct handling of LSL #0 in an IT block
rL297142: [ARM] Correct handling of LSL #0 in an IT block
Summary

The check for LSL #0 in an IT block was checking if operand 4 was zero, but operand 4 is the condition code operand so it was actually checking for LSLEQ. Fix this by checking operand 3, which really is the immediate operand, and add some tests.

Diff Detail

Repository
rL LLVM

Event Timeline

john.brawn created this revision.Mar 7 2017, 6:32 AM
Herald added a subscriber: aemerson. · View Herald TranscriptMar 7 2017, 6:32 AM
olista01 accepted this revision.Mar 7 2017, 6:41 AM
olista01 added a subscriber: olista01.

LGTM

This revision is now accepted and ready to land.Mar 7 2017, 6:41 AM
Closed by commit rL297142: [ARM] Correct handling of LSL #0 in an IT block (authored by john.brawn). · Explain WhyMar 7 2017, 6:54 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
ARM/
AsmParser/
2 lines
test/
MC/
ARM/
14 lines

Diff 90847

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,934 Lines • ▼ Show 20 Lines if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
// in an IT block. // in an IT block.
if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
!inITBlock()) !inITBlock())
return Match_RequiresITBlock; return Match_RequiresITBlock;
if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
inITBlock()) inITBlock())
return Match_RequiresNotITBlock; return Match_RequiresNotITBlock;
// LSL with zero immediate is not allowed in an IT block // LSL with zero immediate is not allowed in an IT block
if (Opc == ARM::tLSLri && Inst.getOperand(4).getImm() == 0 && inITBlock()) if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
return Match_RequiresNotITBlock; return Match_RequiresNotITBlock;
} else if (isThumbOne()) { } else if (isThumbOne()) {
// Some high-register supporting Thumb1 encodings only allow both registers // Some high-register supporting Thumb1 encodings only allow both registers
// to be from r0-r7 when in Thumb2. // to be from r0-r7 when in Thumb2.
if (Opc == ARM::tADDhirr && !hasV6MOps() && if (Opc == ARM::tADDhirr && !hasV6MOps() &&
isARMLowRegister(Inst.getOperand(1).getReg()) && isARMLowRegister(Inst.getOperand(1).getReg()) &&
isARMLowRegister(Inst.getOperand(2).getReg())) isARMLowRegister(Inst.getOperand(2).getReg()))
return Match_RequiresThumb2; return Match_RequiresThumb2;
▲ Show 20 Lines • Show All 1,442 Lines • Show Last 20 Lines

llvm/trunk/test/MC/ARM/lsl-zero.s

Show First 20 Lines • Show All 116 Lines • ▼ Show 20 Lines// CHECK-ARM: mov r0, sp @ encoding: [0x0d,0x00,0xa0,0xe1]
//FIXME: pre-ARMv8 we give an error for these instructions //FIXME: pre-ARMv8 we give an error for these instructions
//mov sp, r0, lsl #0 //mov sp, r0, lsl #0
//mov r0, sp, lsl #0 //mov r0, sp, lsl #0
// LSL #0 in IT block should select the 32-bit encoding // LSL #0 in IT block should select the 32-bit encoding
itt eq itt eq
lsleq r0, r1, #0 lsleq r0, r1, #0
lslseq r0, r1, #0 lslseq r0, r1, #0
itt gt
lslgt r0, r1, #0
lslsgt r0, r1, #0
// CHECK-NONARM: moveq.w r0, r1 @ encoding: [0x4f,0xea,0x01,0x00] // CHECK-NONARM: moveq.w r0, r1 @ encoding: [0x4f,0xea,0x01,0x00]
// CHECK-NONARM: movseq.w r0, r1 @ encoding: [0x5f,0xea,0x01,0x00] // CHECK-NONARM: movseq.w r0, r1 @ encoding: [0x5f,0xea,0x01,0x00]
// CHECK-NONARM: movgt.w r0, r1 @ encoding: [0x4f,0xea,0x01,0x00]
// CHECK-NONARM: movsgt.w r0, r1 @ encoding: [0x5f,0xea,0x01,0x00]
// CHECK-ARM: moveq r0, r1 @ encoding: [0x01,0x00,0xa0,0x01] // CHECK-ARM: moveq r0, r1 @ encoding: [0x01,0x00,0xa0,0x01]
// CHECK-ARM: movseq r0, r1 @ encoding: [0x01,0x00,0xb0,0x01] // CHECK-ARM: movseq r0, r1 @ encoding: [0x01,0x00,0xb0,0x01]
// CHECK-ARM: movgt r0, r1 @ encoding: [0x01,0x00,0xa0,0xc1]
// CHECK-ARM: movsgt r0, r1 @ encoding: [0x01,0x00,0xb0,0xc1]
itt eq itt eq
moveq r0, r1, lsl #0 moveq r0, r1, lsl #0
movseq r0, r1, lsl #0 movseq r0, r1, lsl #0
itt gt
movgt r0, r1, lsl #0
movsgt r0, r1, lsl #0
// CHECK-NONARM: moveq.w r0, r1 @ encoding: [0x4f,0xea,0x01,0x00] // CHECK-NONARM: moveq.w r0, r1 @ encoding: [0x4f,0xea,0x01,0x00]
// CHECK-NONARM: movseq.w r0, r1 @ encoding: [0x5f,0xea,0x01,0x00] // CHECK-NONARM: movseq.w r0, r1 @ encoding: [0x5f,0xea,0x01,0x00]
// CHECK-NONARM: movgt.w r0, r1 @ encoding: [0x4f,0xea,0x01,0x00]
// CHECK-NONARM: movsgt.w r0, r1 @ encoding: [0x5f,0xea,0x01,0x00]
// CHECK-ARM: moveq r0, r1 @ encoding: [0x01,0x00,0xa0,0x01] // CHECK-ARM: moveq r0, r1 @ encoding: [0x01,0x00,0xa0,0x01]
// CHECK-ARM: movseq r0, r1 @ encoding: [0x01,0x00,0xb0,0x01] // CHECK-ARM: movseq r0, r1 @ encoding: [0x01,0x00,0xb0,0x01]
// CHECK-ARM: movgt r0, r1 @ encoding: [0x01,0x00,0xa0,0xc1]
// CHECK-ARM: movsgt r0, r1 @ encoding: [0x01,0x00,0xb0,0xc1]