In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn't live.

[tyomitch]

Summary

Previously, it had always been materialized as a push/pop sequence.

[jroelofs]

LGTM with one small nit.

test/CodeGen/Thumb/copy_thumb.ll

27

Please add a testcase for v4t and v5t that has CPSR live, so as to test the behavior in the other branch.

[tyomitch]

Updated test/CodeGen/ARM/smml.ll to check the handling of live CPSR (and cleaned up the CHECKs in general)

[jroelofs]

awesome, thanks.

test/CodeGen/ARM/smml.ll

47 ↗

(On Diff #90710)

Interesting that CPSR is only live here because the cmp happens before where we wanted the movs.

lib/Target/ARM/Thumb1InstrInfo.cpp

assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
          "Thumb1 can only copy GPR registers");
 
   if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
       || !ARM::tGPRRegClass.contains(DestReg))
     BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc))
         .add(predOps(ARMCC::AL));
   else {
-    // FIXME: The performance consequences of this are going to be atrocious.
-    // Some things to try that should be better:
-    //   * 'mov hi, $src; mov $dst, hi', with hi as either r10 or r11
-    //   * 'movs $dst, $src' if cpsr isn't live
-    // See: http://lists.llvm.org/pipermail/llvm-dev/2014-August/075998.html
+    // FIXME: Can also use 'mov hi, $src; mov $dst, hi',
+    // with hi as either r10 or r11.
+
+    const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
+    if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
+        == MachineBasicBlock::LQR_Dead) {
+      BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
+          .addReg(SrcReg, getKillRegState(KillSrc))
+          ->addRegisterDead(ARM::CPSR, RegInfo);
+      return;
+    }
 
     // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
     BuildMI(MBB, I, DL, get(ARM::tPUSH))
         .add(predOps(ARMCC::AL))
         .addReg(SrcReg, getKillRegState(KillSrc));
     BuildMI(MBB, I, DL, get(ARM::tPOP))
         .add(predOps(ARMCC::AL))
         .addReg(DestReg, getDefRegState(true));

test/CodeGen/ARM/arm-and-tst-peephole.ll

 ; ARM:       @ BB#0:
 ; ARM-NEXT:    and r0, r0, #1
 ; ARM-NEXT:    tst r1, #1
 ; ARM-NEXT:    subne r0, r0, #1
 ; ARM-NEXT:    mov pc, lr
 ;
 ; THUMB-LABEL: test_tst_assessment:
 ; THUMB:       @ BB#0:
-; THUMB-NEXT:    push {r0}
-; THUMB-NEXT:    pop {r2}
+; THUMB-NEXT:    movs r2, r0
 ; THUMB-NEXT:    movs r0, #1
 ; THUMB-NEXT:    ands r0, r2
 ; THUMB-NEXT:    subs r2, r0, #1
 ; THUMB-NEXT:    lsls r1, r1, #31
 ; THUMB-NEXT:    beq .LBB2_2
 ; THUMB-NEXT:  @ BB#1:
-; THUMB-NEXT:    push {r2}
-; THUMB-NEXT:    pop {r0}
+; THUMB-NEXT:    movs r0, r2
 ; THUMB-NEXT:  .LBB2_2:
 ; THUMB-NEXT:    bx lr
 ;
 ; T2-LABEL: test_tst_assessment:
 ; T2:       @ BB#0:
 ; T2-NEXT:    lsls r1, r1, #31
 ; T2-NEXT:    and r0, r0, #1
 ; T2-NEXT:    it ne

test/CodeGen/ARM/atomic-cmpxchg.ll

 ; CHECK-ARM: mov [[REG:r[0-9]+]], #0
 ; CHECK-ARM: cmp r0, {{r[0-9]+}}
 ; CHECK-ARM: moveq [[REG]], #1
 ; CHECK-ARM: mov r0, [[REG]]
 
 ; CHECK-THUMB-LABEL: test_cmpxchg_res_i8
 ; CHECK-THUMB: bl __sync_val_compare_and_swap_1
 ; CHECK-THUMB-NOT: mov [[R1:r[0-7]]], r0
-; CHECK-THUMB: push  {r0}
-; CHECK-THUMB: pop {[[R1:r[0-7]]]}
+; CHECK-THUMB: movs [[R1:r[0-7]]], r0
 ; CHECK-THUMB: movs r0, #1
 ; CHECK-THUMB: movs [[R2:r[0-9]+]], #0
 ; CHECK-THUMB: cmp [[R1]], {{r[0-9]+}}
 ; CHECK-THUMB: beq
-; CHECK-THUMB: push  {[[R2]]}
-; CHECK-THUMB: pop {r0}
+; CHECK-THUMB: movs r0, [[R2]]
 
 ; CHECK-ARMV6-LABEL: test_cmpxchg_res_i8:
 ; CHECK-ARMV6-NEXT:  .fnstart
 ; CHECK-ARMV6-NEXT: uxtb [[DESIRED:r[0-9]+]], r1
 ; CHECK-ARMV6-NEXT: [[TRY:.LBB[0-9_]+]]:
 ; CHECK-ARMV6-NEXT: ldrexb [[LD:r[0-9]+]], [r0]
 ; CHECK-ARMV6-NEXT: cmp [[LD]], [[DESIRED]]
 ; CHECK-ARMV6-NEXT: movne [[RES:r[0-9]+]], #0

test/CodeGen/Thumb/copy_thumb.ll

 ; CHECK-LOLOMOV-NEXT:   mov [[SRC2]], [[TMP]]
 ; CHECK-LOLOMOV-LABEL:  bar
 ; CHECK-LOLOMOV-LABEL:  fnend
 ; 
 ; 'MOV lo, lo' in Thumb mode produces undefined results on pre-v6 hardware
 ; RUN: llc -mtriple=thumbv4t-none--eabi < %s | FileCheck %s --check-prefix=CHECK-NOLOLOMOV
 ; RUN: llc -mtriple=thumbv5-none--eabi < %s | FileCheck %s --check-prefix=CHECK-NOLOLOMOV
 ; CHECK-NOLOLOMOV-LABEL: foo
-; CHECK-NOLOLOMOV-NOT:   mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
-; CHECK-NOLOLOMOV:       push  {[[SRC1:r[01]]]}
-; CHECK-NOLOLOMOV-NEXT:  pop {[[TMP:r[0-7]]]}
-; CHECK-NOLOLOMOV-NOT:   mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
-; CHECK-NOLOLOMOV:       push  {[[SRC2:r[01]]]}
-; CHECK-NOLOLOMOV-NEXT:  pop {[[SRC1]]}
-; CHECK-NOLOLOMOV-NOT:   mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
-; CHECK-NOLOLOMOV:       push  {[[TMP]]}
-; CHECK-NOLOLOMOV-NEXT:  pop {[[SRC2]]}
+; CHECK-NOLOLOMOV:       movs [[TMP:r[0-7]]], [[SRC1:r[01]]]
+; CHECK-NOLOLOMOV-NEXT:  movs [[SRC1]], [[SRC2:r[01]]]
+; CHECK-NOLOLOMOV-NEXT:  movs [[SRC2]], [[TMP]]
 ; CHECK-NOLOLOMOV-LABEL: bar
 ; CHECK-NOLOLOMOV-LABEL: fnend
 
 declare void @bar(i32, i32)
 
 define void @foo(i32 %a, i32 %b) {
 entry:
   call void @bar(i32 %b, i32 %a);
   ret void
 }
 

test/CodeGen/Thumb/thumb-shrink-wrapping.ll

 ; DISABLE: cmp r0, #0
 ; DISABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]]
 ;
 ; Setup of the varags.
 ; CHECK: mov [[TMP_SP:r[0-9]+]], sp
 ; CHECK-NEXT: str r1, {{\[}}[[TMP_SP]]]
 ; CHECK-NEXT: str r1, {{\[}}[[TMP_SP]], #4]
 ; CHECK-NEXT: str r1, {{\[}}[[TMP_SP]], #8]
-; Thumb has quite a strange way for moving stuff
-; in around. Oh well, match the current sequence.
-; CHECK: push {r1}
-; CHECK-NEXT: pop {r0}
-; CHECK: push {r1}
-; CHECK-NEXT: pop {r2}
-; CHECK: push {r1}
-; CHECK-NEXT: pop {r3}
+; CHECK:      movs r0, r1
+; CHECK-NEXT: movs r2, r1
+; CHECK-NEXT: movs r3, r1
 ; CHECK-NEXT: bl
 ; CHECK-NEXT: lsls r0, r0, #3
 ;
 ; ENABLE-NEXT: add sp, #16
 ; ENABLE-V5T-NEXT: pop {[[TMP]], pc}
 ; ENABLE-V4T-NEXT: pop {[[TMP]]}
 ; ENABLE-V4T-NEXT: pop {r1}
 ; ENABLE-V4T-NEXT: bx r1