[DAGCombine] Simplify ISD::AND in GetDemandedBits.

[efriedma]

Summary

This helps in cases involving bitfields where an AND is exposed by legalization.

[RKSimon]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7477

How often are cases from each operand occurring? Since we canonicalize constants to the RHS would it be performant to test that first?

[spatel]

It's not this patch's fault of course, but that set -> sbb transform looks like a regression for every CPU that I checked in Agner's tables (sbb has higher latency and/or less throughput).
Should we fix that first?

[efriedma]

How often are cases from each operand occurring? Since we canonicalize constants to the RHS would it be performant to test that first?

The cases affected here are all AND with a constant mask. Should I special-case constants, or just rearrange order of the checks?

It's not this patch's fault of course, but that set -> sbb transform looks like a regression for every CPU that I checked in Agner's tables (sbb has higher latency and/or less throughput). Should we fix that first?

I took a brief look, but there isn't any obvious cause. Maybe some x86 combine interacting badly with the fact that AVX-512 makes i1 a legal type.

[spatel]

In D30472#689093, @efriedma wrote:

I took a brief look, but there isn't any obvious cause. Maybe some x86 combine interacting badly with the fact that AVX-512 makes i1 a legal type.

No problem - I'm rummaging around down here, so I'll try to find it. I don't think bogus sbb lowering is worth holding up this patch. Once Simon's concern is addressed, this should be good.

[RKSimon]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7477

Does this still work with a check using isConstOrConstSplat(V.getOperand(1)) ? If so I'd go with that as what you have right now is probably overkill.

[efriedma]

Don't call ComputeMaskedBits; just check for a constant.

[RKSimon]

LGTM with one minor

test/CodeGen/X86/illegal-bitfield-loadstore.ll

94

Please can you remove the old ACHECK lines? The update script won't touch comments it doesn't recognise, including unknown filecheck prefixes.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N0.getOpcode() == ISD::AssertZext &&
     return N0;
 
   return SDValue();
 }
 
 /// See if the specified operand can be simplified with the knowledge that only
 /// the bits specified by Mask are used.  If so, return the simpler operand,
 /// otherwise return a null SDValue.
+///
+/// (This exists alongside SimplifyDemandedBits because GetDemandedBits can
+/// simplify nodes with multiple uses more aggressively.)
 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
   switch (V.getOpcode()) {
   default: break;
   case ISD::Constant: {
     const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
     assert(CV && "Const value should be ConstSDNode.");
     const APInt &CVal = CV->getAPIntValue();
     APInt NewVal = CVal & Mask;
if (ConstantSDNode *RHSC = getAsNonOpaqueConstant(V.getOperand(1))) {
 
       // Watch out for shift count overflow though.
       if (Amt >= Mask.getBitWidth()) break;
       APInt NewMask = Mask << Amt;
       if (SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask))
         return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
                            SimplifyLHS, V.getOperand(1));
     }
+    break;
+  case ISD::AND: {
+    // X & -1 -> X (ignoring bits which aren't demanded).
+    ConstantSDNode *AndVal = isConstOrConstSplat(V.getOperand(1));
+    if (AndVal && (AndVal->getAPIntValue() & Mask) == Mask)
+      return V.getOperand(0);
+    break;
+  }
   }
   return SDValue();
 }
 
 /// If the result of a wider load is shifted to right of N  bits and then
 /// truncated to a narrower type and where N is a multiple of number of bits of
 /// the narrower type, transform it to a narrower load from address + N / num of
 /// bits of new type. If the result is to be extended, also fold the extension

test/CodeGen/ARM/illegal-bitfield-loadstore.ll

; BE-NEXT:    mov pc, lr
   %b = or i24 %aa, 384
   store i24 %b, i24* %a, align 1
   ret void
 }
 
 define void @i24_and_or(i24* %a) {
 ; LE-LABEL: i24_and_or:
 ; LE:       @ BB#0:
-; LE-NEXT:    ldrb r1, [r0, #2]
-; LE-NEXT:    ldrh r2, [r0]
-; LE-NEXT:    orr r1, r2, r1, lsl #16
-; LE-NEXT:    ldr r2, .LCPI1_0
+; LE-NEXT:    ldrb r2, [r0, #2]
+; LE-NEXT:    ldrh r1, [r0]
+; LE-NEXT:    strb r2, [r0, #2]
+; LE-NEXT:    mov r2, #16256
 ; LE-NEXT:    orr r1, r1, #384
+; LE-NEXT:    orr r2, r2, #49152
 ; LE-NEXT:    and r1, r1, r2
 ; LE-NEXT:    strh r1, [r0]
-; LE-NEXT:    lsr r1, r1, #16
-; LE-NEXT:    strb r1, [r0, #2]
 ; LE-NEXT:    mov pc, lr
-; LE-NEXT:    .p2align 2
-; LE-NEXT:  @ BB#1:
-; LE-NEXT:  .LCPI1_0:
-; LE-NEXT:    .long 16777088 @ 0xffff80
 ;
 ; BE-LABEL: i24_and_or:
 ; BE:       @ BB#0:
 ; BE-NEXT:    ldrh r1, [r0]
-; BE-NEXT:    mov r2, #384
-; BE-NEXT:    orr r1, r2, r1, lsl #8
-; BE-NEXT:    ldr r2, .LCPI1_0
-; BE-NEXT:    and r1, r1, r2
-; BE-NEXT:    strb r1, [r0, #2]
-; BE-NEXT:    lsr r1, r1, #8
+; BE-NEXT:    mov r2, #128
+; BE-NEXT:    strb r2, [r0, #2]
+; BE-NEXT:    orr r1, r1, #1
 ; BE-NEXT:    strh r1, [r0]
 ; BE-NEXT:    mov pc, lr
-; BE-NEXT:    .p2align 2
-; BE-NEXT:  @ BB#1:
-; BE-NEXT:  .LCPI1_0:
-; BE-NEXT:    .long 16777088 @ 0xffff80
   %b = load i24, i24* %a, align 1
   %c = and i24 %b, -128
   %d = or i24 %c, 384
   store i24 %d, i24* %a, align 1
   ret void
 }
 
 define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
 ; LE-LABEL: i24_insert_bit:
 ; LE:       @ BB#0:
-; LE-NEXT:    ldrb r2, [r0, #2]
-; LE-NEXT:    ldrh r3, [r0]
-; LE-NEXT:    orr r2, r3, r2, lsl #16
-; LE-NEXT:    ldr r3, .LCPI2_0
+; LE-NEXT:    ldrb r3, [r0, #2]
+; LE-NEXT:    ldrh r2, [r0]
+; LE-NEXT:    strb r3, [r0, #2]
+; LE-NEXT:    mov r3, #255
+; LE-NEXT:    orr r3, r3, #57088
 ; LE-NEXT:    and r2, r2, r3
-; LE-NEXT:    lsr r3, r2, #16
 ; LE-NEXT:    orr r1, r2, r1, lsl #13
-; LE-NEXT:    strb r3, [r0, #2]
 ; LE-NEXT:    strh r1, [r0]
 ; LE-NEXT:    mov pc, lr
-; LE-NEXT:    .p2align 2
-; LE-NEXT:  @ BB#1:
-; LE-NEXT:  .LCPI2_0:
-; LE-NEXT:    .long 16769023 @ 0xffdfff
 ;
 ; BE-LABEL: i24_insert_bit:
 ; BE:       @ BB#0:
-; BE-NEXT:    ldrh r2, [r0]
 ; BE-NEXT:    ldrb r3, [r0, #2]
-; BE-NEXT:    orr r2, r3, r2, lsl #8
-; BE-NEXT:    ldr r3, .LCPI2_0
-; BE-NEXT:    and r2, r2, r3
+; BE-NEXT:    ldrh r2, [r0]
+; BE-NEXT:    strb r3, [r0, #2]
+; BE-NEXT:    mov r3, #57088
+; BE-NEXT:    orr r3, r3, #16711680
+; BE-NEXT:    and r2, r3, r2, lsl #8
 ; BE-NEXT:    orr r1, r2, r1, lsl #13
-; BE-NEXT:    strb r2, [r0, #2]
 ; BE-NEXT:    lsr r1, r1, #8
 ; BE-NEXT:    strh r1, [r0]
 ; BE-NEXT:    mov pc, lr
-; BE-NEXT:    .p2align 2
-; BE-NEXT:  @ BB#1:
-; BE-NEXT:  .LCPI2_0:
-; BE-NEXT:    .long 16769023 @ 0xffdfff
   %extbit = zext i1 %bit to i24
   %b = load i24, i24* %a, align 1
   %extbit.shl = shl nuw nsw i24 %extbit, 13
   %c = and i24 %b, -8193
   %d = or i24 %c, %extbit.shl
   store i24 %d, i24* %a, align 1
   ret void
 }

 ; LE-NEXT:    strh r12, [r3]
 ; LE-NEXT:    pop {r11, lr}
 ; LE-NEXT:    mov pc, lr
 ;
 ; BE-LABEL: i56_insert_bit:
 ; BE:       @ BB#0:
 ; BE-NEXT:    .save {r11, lr}
 ; BE-NEXT:    push {r11, lr}
-; BE-NEXT:    mov r2, r0
+; BE-NEXT:    mov r3, r0
 ; BE-NEXT:    ldr lr, [r0]
-; BE-NEXT:    ldrh r12, [r2, #4]!
-; BE-NEXT:    ldrb r3, [r2, #2]
-; BE-NEXT:    orr r12, r3, r12, lsl #8
-; BE-NEXT:    orr r3, r12, lr, lsl #24
-; BE-NEXT:    bic r3, r3, #8192
-; BE-NEXT:    orr r1, r3, r1, lsl #13
-; BE-NEXT:    strb r3, [r2, #2]
-; BE-NEXT:    lsr r3, r1, #8
-; BE-NEXT:    strh r3, [r2]
+; BE-NEXT:    ldrh r12, [r3, #4]!
+; BE-NEXT:    ldrb r2, [r3, #2]
+; BE-NEXT:    strb r2, [r3, #2]
+; BE-NEXT:    orr r2, r2, r12, lsl #8
+; BE-NEXT:    orr r2, r2, lr, lsl #24
+; BE-NEXT:    bic r2, r2, #8192
+; BE-NEXT:    orr r1, r2, r1, lsl #13
+; BE-NEXT:    lsr r2, r1, #8
+; BE-NEXT:    strh r2, [r3]
 ; BE-NEXT:    bic r2, lr, #255
 ; BE-NEXT:    orr r1, r2, r1, lsr #24
 ; BE-NEXT:    str r1, [r0]
 ; BE-NEXT:    pop {r11, lr}
 ; BE-NEXT:    mov pc, lr
   %extbit = zext i1 %bit to i56
   %b = load i56, i56* %a, align 1
   %extbit.shl = shl nuw nsw i56 %extbit, 13
   %c = and i56 %b, -8193
   %d = or i56 %c, %extbit.shl
   store i56 %d, i56* %a, align 1
   ret void
 }
 

test/CodeGen/X86/avx512-insert-extract.ll

; SKX-NEXT:    retq
   %res = select i1 %extract24vector_func.i, i64 %a1, i64 %b1
   ret i64 %res
 }
 
 define i16 @test13(i32 %a, i32 %b) {
 ; KNL-LABEL: test13:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    cmpl %esi, %edi
-; KNL-NEXT:    setb %al
+; KNL-NEXT:    sbbb %al, %al
 ; KNL-NEXT:    andl $1, %eax
 ; KNL-NEXT:    kmovw %eax, %k0
 ; KNL-NEXT:    movw $-4, %ax
 ; KNL-NEXT:    kmovw %eax, %k1
 ; KNL-NEXT:    kshiftrw $1, %k1, %k1
 ; KNL-NEXT:    kshiftlw $1, %k1, %k1
 ; KNL-NEXT:    korw %k0, %k1, %k0
 ; KNL-NEXT:    kmovw %k0, %eax
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: test13:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    cmpl %esi, %edi
-; SKX-NEXT:    setb %al
+; SKX-NEXT:    sbbb %al, %al
 ; SKX-NEXT:    andl $1, %eax
 ; SKX-NEXT:    kmovw %eax, %k0
 ; SKX-NEXT:    movw $-4, %ax
 ; SKX-NEXT:    kmovw %eax, %k1
 ; SKX-NEXT:    kshiftrw $1, %k1, %k1
 ; SKX-NEXT:    kshiftlw $1, %k1, %k1
 ; SKX-NEXT:    korw %k0, %k1, %k0
 ; SKX-NEXT:    kmovw %k0, %eax

 ; KNL-NEXT:    movl (%rsp), %eax
 ; KNL-NEXT:    movq %rbp, %rsp
 ; KNL-NEXT:    popq %rbp
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: test_insertelement_v32i1:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    cmpl %esi, %edi
-; SKX-NEXT:    setb %al
+; SKX-NEXT:    sbbb %al, %al
 ; SKX-NEXT:    andl $1, %eax
 ; SKX-NEXT:    kmovw %eax, %k0
 ; SKX-NEXT:    vpcmpltud %zmm2, %zmm0, %k1
 ; SKX-NEXT:    vpcmpltud %zmm3, %zmm1, %k2
 ; SKX-NEXT:    kunpckwd %k1, %k2, %k1
 ; SKX-NEXT:    vpmovm2w %k1, %zmm0
 ; SKX-NEXT:    vpmovm2w %k0, %zmm1
 ; SKX-NEXT:    vmovdqu16 {{.*#+}} zmm2 = [0,1,2,3,32,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
 ; SKX-NEXT:    vpermi2w %zmm1, %zmm0, %zmm2
 ; SKX-NEXT:    vpmovw2m %zmm2, %k0
 ; SKX-NEXT:    kmovd %k0, %eax
 ; SKX-NEXT:    vzeroupper
 ; SKX-NEXT:    retq
   %cmp_res_i1 = icmp ult i32 %a, %b
   %cmp_cmp_vec = icmp ult <32 x i32> %x, %y
   %maskv = insertelement <32 x i1> %cmp_cmp_vec, i1 %cmp_res_i1, i32 4
   %res = bitcast <32 x i1> %maskv to i32
   ret i32 %res
 }
 
 define i8 @test_iinsertelement_v4i1(i32 %a, i32 %b, <4 x i32> %x , <4 x i32> %y) {
 ; KNL-LABEL: test_iinsertelement_v4i1:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    cmpl %esi, %edi
-; KNL-NEXT:    setb %al
+; KNL-NEXT:    sbbb %al, %al
 ; KNL-NEXT:    andl $1, %eax
 ; KNL-NEXT:    kmovw %eax, %k1
 ; KNL-NEXT:    vpbroadcastd {{.*}}(%rip), %xmm2
 ; KNL-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; KNL-NEXT:    vpxor %xmm2, %xmm1, %xmm1
 ; KNL-NEXT:    vpcmpgtd %xmm0, %xmm1, %xmm0
 ; KNL-NEXT:    vpextrd $1, %xmm0, %eax
 ; KNL-NEXT:    andl $1, %eax

 ; KNL-NEXT:    vpsllq $63, %zmm2, %zmm0
 ; KNL-NEXT:    vptestmq %zmm0, %zmm0, %k0
 ; KNL-NEXT:    kmovw %k0, %eax
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: test_iinsertelement_v4i1:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    cmpl %esi, %edi
-; SKX-NEXT:    setb %al
+; SKX-NEXT:    sbbb %al, %al
 ; SKX-NEXT:    andl $1, %eax
 ; SKX-NEXT:    kmovw %eax, %k0
 ; SKX-NEXT:    vpcmpltud %xmm1, %xmm0, %k1
 ; SKX-NEXT:    vpmovm2d %k1, %xmm0
 ; SKX-NEXT:    vpmovm2d %k0, %xmm1
 ; SKX-NEXT:    vpbroadcastq %xmm1, %xmm1
 ; SKX-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
 ; SKX-NEXT:    vpmovd2m %xmm0, %k0
 ; SKX-NEXT:    kmovb %k0, %eax
 ; SKX-NEXT:    retq
   %cmp_res_i1 = icmp ult i32 %a, %b
   %cmp_cmp_vec = icmp ult <4 x i32> %x, %y
   %maskv = insertelement <4 x i1> %cmp_cmp_vec, i1 %cmp_res_i1, i32 2
   %res0 = shufflevector <4 x i1> %maskv, <4 x i1> undef , <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
   %res = bitcast <8 x i1> %res0 to i8
   ret i8 %res
 }
 
 define i8 @test_iinsertelement_v2i1(i32 %a, i32 %b, <2 x i64> %x , <2 x i64> %y) {
 ; KNL-LABEL: test_iinsertelement_v2i1:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    cmpl %esi, %edi
-; KNL-NEXT:    setb %al
+; KNL-NEXT:    sbbb %al, %al
 ; KNL-NEXT:    andl $1, %eax
 ; KNL-NEXT:    kmovw %eax, %k1
 ; KNL-NEXT:    vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
 ; KNL-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; KNL-NEXT:    vpxor %xmm2, %xmm1, %xmm1
 ; KNL-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm0
 ; KNL-NEXT:    vmovq %xmm0, %rax
 ; KNL-NEXT:    andl $1, %eax
 ; KNL-NEXT:    kmovw %eax, %k2
 ; KNL-NEXT:    vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k2} {z}
 ; KNL-NEXT:    vpternlogq $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
 ; KNL-NEXT:    vmovdqa64 {{.*#+}} zmm2 = [0,8,2,3,4,5,6,7]
 ; KNL-NEXT:    vpermi2q %zmm1, %zmm0, %zmm2
 ; KNL-NEXT:    vpsllq $63, %zmm2, %zmm0
 ; KNL-NEXT:    vptestmq %zmm0, %zmm0, %k0
 ; KNL-NEXT:    kmovw %k0, %eax
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: test_iinsertelement_v2i1:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    cmpl %esi, %edi
-; SKX-NEXT:    setb %al
+; SKX-NEXT:    sbbb %al, %al
 ; SKX-NEXT:    andl $1, %eax
 ; SKX-NEXT:    kmovw %eax, %k0
 ; SKX-NEXT:    vpcmpltuq %xmm1, %xmm0, %k1
 ; SKX-NEXT:    kshiftlw $1, %k1, %k1
 ; SKX-NEXT:    kshiftrw $1, %k1, %k1
 ; SKX-NEXT:    kshiftlw $1, %k0, %k0
 ; SKX-NEXT:    korw %k0, %k1, %k0
 ; SKX-NEXT:    kmovb %k0, %eax

test/CodeGen/X86/illegal-bitfield-loadstore.ll

; CHECK-NEXT:    retq
   ret void
 }
 
 define void @i24_and_or(i24* %a) {
 ; CHECK-LABEL: i24_and_or:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    movzwl (%rdi), %eax
 ; CHECK-NEXT:    movzbl 2(%rdi), %ecx
+; CHECK-NEXT:    movb %cl, 2(%rdi)
 ; CHECK-NEXT:    shll $16, %ecx
 ; CHECK-NEXT:    orl %eax, %ecx
 ; CHECK-NEXT:    orl $384, %ecx # imm = 0x180
 ; CHECK-NEXT:    andl $16777088, %ecx # imm = 0xFFFF80
 ; CHECK-NEXT:    movw %cx, (%rdi)
-; CHECK-NEXT:    shrl $16, %ecx
-; CHECK-NEXT:    movb %cl, 2(%rdi)
 ; CHECK-NEXT:    retq
   %b = load i24, i24* %a, align 1
   %c = and i24 %b, -128
   %d = or i24 %c, 384
   store i24 %d, i24* %a, align 1
   ret void
 }
 
 define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
 ; CHECK-LABEL: i24_insert_bit:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    movzbl %sil, %eax
 ; CHECK-NEXT:    movzwl (%rdi), %ecx
 ; CHECK-NEXT:    movzbl 2(%rdi), %edx
+; CHECK-NEXT:    movb %dl, 2(%rdi)
 ; CHECK-NEXT:    shll $16, %edx
 ; CHECK-NEXT:    orl %ecx, %edx
 ; CHECK-NEXT:    shll $13, %eax
 ; CHECK-NEXT:    andl $16769023, %edx # imm = 0xFFDFFF
-; CHECK-NEXT:    orl %edx, %eax
-; CHECK-NEXT:    shrl $16, %edx
-; CHECK-NEXT:    movb %dl, 2(%rdi)
-; CHECK-NEXT:    movw %ax, (%rdi)
+; CHECK-NEXT:    orl %eax, %edx
+; CHECK-NEXT:    movw %dx, (%rdi)
 ; CHECK-NEXT:    retq
   %extbit = zext i1 %bit to i24
   %b = load i24, i24* %a, align 1
   %extbit.shl = shl nuw nsw i24 %extbit, 13
   %c = and i24 %b, -8193
   %d = or i24 %c, %extbit.shl
   store i24 %d, i24* %a, align 1
   ret void
 }
 
 define void @i56_or(i56* %a) {
 ; CHECK-LABEL: i56_or:
 ; CHECK:       # BB#0:
+; CHECK-NEXT:    movzwl 4(%rdi), %eax
+; CHECK-NEXT:    movzbl 6(%rdi), %ecx
+; CHECK-NEXT:    movl (%rdi), %edx
+; CHECK-NEXT:    movb %cl, 6(%rdi)
+; CHECK-NEXT:    # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
+; CHECK-NEXT:    shll $16, %ecx
+; CHECK-NEXT:    orl %eax, %ecx
+; CHECK-NEXT:    shlq $32, %rcx
+; CHECK-NEXT:    orq %rcx, %rdx
+; CHECK-NEXT:    orq $384, %rdx # imm = 0x180
+; CHECK-NEXT:    movl %edx, (%rdi)
+; CHECK-NEXT:    shrq $32, %rdx
+; CHECK-NEXT:    movw %dx, 4(%rdi)
+; CHECK-NEXT:    retq
 ; ACHECK-NEXT:    movzwl 4(%rdi), %eax
 ; ACHECK-NEXT:    movzbl 6(%rdi), %ecx
 ; ACHECK-NEXT:    movl (%rdi), %edx
 ; ACHECK-NEXT:    movb %cl, 6(%rdi)
 ; ACHECK-NEXT:    # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
 ; ACHECK-NEXT:    shll $16, %ecx
 ; ACHECK-NEXT:    orl %eax, %ecx
 ; ACHECK-NEXT:    shlq $32, %rcx
 ; ACHECK-NEXT:    orq %rcx, %rdx
 ; ACHECK-NEXT:    orq $384, %rdx # imm = 0x180
 ; ACHECK-NEXT:    movl %edx, (%rdi)
 ; ACHECK-NEXT:    shrq $32, %rdx
 ; ACHECK-NEXT:    movw %dx, 4(%rdi)
 ; ACHECK-NEXT:    retq
   %aa = load i56, i56* %a, align 1
   %b = or i56 %aa, 384
   store i56 %b, i56* %a, align 1
   ret void
 }
 
 define void @i56_and_or(i56* %a) {
 ; CHECK-LABEL: i56_and_or:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    movzwl 4(%rdi), %eax
 ; CHECK-NEXT:    movzbl 6(%rdi), %ecx
+; CHECK-NEXT:    movl (%rdi), %edx
+; CHECK-NEXT:    movb %cl, 6(%rdi)
+; CHECK-NEXT:    # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
 ; CHECK-NEXT:    shll $16, %ecx
 ; CHECK-NEXT:    orl %eax, %ecx
 ; CHECK-NEXT:    shlq $32, %rcx
-; CHECK-NEXT:    movl (%rdi), %eax
-; CHECK-NEXT:    orq %rcx, %rax
-; CHECK-NEXT:    orq $384, %rax # imm = 0x180
-; CHECK-NEXT:    movabsq $72057594037927808, %rcx # imm = 0xFFFFFFFFFFFF80
-; CHECK-NEXT:    andq %rax, %rcx
-; CHECK-NEXT:    movl %ecx, (%rdi)
-; CHECK-NEXT:    movq %rcx, %rax
-; CHECK-NEXT:    shrq $48, %rax
-; CHECK-NEXT:    movb %al, 6(%rdi)
-; CHECK-NEXT:    shrq $32, %rcx
-; CHECK-NEXT:    movw %cx, 4(%rdi)
+; CHECK-NEXT:    orq %rcx, %rdx
+; CHECK-NEXT:    orq $384, %rdx # imm = 0x180
+; CHECK-NEXT:    movabsq $72057594037927808, %rax # imm = 0xFFFFFFFFFFFF80
+; CHECK-NEXT:    andq %rdx, %rax
+; CHECK-NEXT:    movl %eax, (%rdi)
+; CHECK-NEXT:    shrq $32, %rax
+; CHECK-NEXT:    movw %ax, 4(%rdi)
 ; CHECK-NEXT:    retq
   %b = load i56, i56* %a, align 1
   %c = and i56 %b, -128
   %d = or i56 %c, 384
   store i56 %d, i56* %a, align 1
   ret void
 }
 
 define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {
 ; CHECK-LABEL: i56_insert_bit:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    movzbl %sil, %eax
 ; CHECK-NEXT:    movzwl 4(%rdi), %ecx
 ; CHECK-NEXT:    movzbl 6(%rdi), %edx
+; CHECK-NEXT:    movl (%rdi), %esi
+; CHECK-NEXT:    movb %dl, 6(%rdi)
+; CHECK-NEXT:    # kill: %EDX<def> %EDX<kill> %RDX<kill> %RDX<def>
 ; CHECK-NEXT:    shll $16, %edx
 ; CHECK-NEXT:    orl %ecx, %edx
 ; CHECK-NEXT:    shlq $32, %rdx
-; CHECK-NEXT:    movl (%rdi), %ecx
-; CHECK-NEXT:    orq %rdx, %rcx
+; CHECK-NEXT:    orq %rdx, %rsi
 ; CHECK-NEXT:    shlq $13, %rax
-; CHECK-NEXT:    movabsq $72057594037919743, %rdx # imm = 0xFFFFFFFFFFDFFF
-; CHECK-NEXT:    andq %rcx, %rdx
-; CHECK-NEXT:    orq %rdx, %rax
-; CHECK-NEXT:    shrq $48, %rdx
-; CHECK-NEXT:    movb %dl, 6(%rdi)
-; CHECK-NEXT:    movl %eax, (%rdi)
-; CHECK-NEXT:    shrq $32, %rax
-; CHECK-NEXT:    movw %ax, 4(%rdi)
+; CHECK-NEXT:    movabsq $72057594037919743, %rcx # imm = 0xFFFFFFFFFFDFFF
+; CHECK-NEXT:    andq %rsi, %rcx
+; CHECK-NEXT:    orq %rax, %rcx
+; CHECK-NEXT:    movl %ecx, (%rdi)
+; CHECK-NEXT:    shrq $32, %rcx
+; CHECK-NEXT:    movw %cx, 4(%rdi)
 ; CHECK-NEXT:    retq
   %extbit = zext i1 %bit to i56
   %b = load i56, i56* %a, align 1
   %extbit.shl = shl nuw nsw i56 %extbit, 13
   %c = and i56 %b, -8193
   %d = or i56 %c, %extbit.shl
   store i56 %d, i56* %a, align 1
   ret void
 }
 

test/CodeGen/X86/xaluo.ll

 ; KNL-NEXT:    sbbb %dl, %dl
 ; KNL-NEXT:    movq $-1, %rax
 ; KNL-NEXT:    subq %rsi, %rax
 ; KNL-NEXT:    sbbb %cl, %cl
 ; KNL-NEXT:    orb %dl, %cl
 ; KNL-NEXT:    subq %rdi, %rax
 ; KNL-NEXT:    sbbb %dl, %dl
 ; KNL-NEXT:    orb %cl, %dl
-; KNL-NEXT:    andb $1, %dl
 ; KNL-NEXT:    retq
   %t0 = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %a)
   %v0 = extractvalue {i64, i1} %t0, 0
   %o0 = extractvalue {i64, i1} %t0, 1
   %t1 = call {i64, i1} @llvm.usub.with.overflow.i64(i64 -1, i64 %b)
   %v1 = extractvalue {i64, i1} %t1, 0
   %o1 = extractvalue {i64, i1} %t1, 1
   %oo = or i1 %o0, %o1