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Differential D30126

AMDGPU: Fix disassembly of aperture registers
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Authored by arsenm on Feb 17 2017, 4:35 PM.

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kzhuravl

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arsenm created this revision.Feb 17 2017, 4:35 PM

Herald added subscribers: tpr, tony-tye, yaxunl and 3 others. · View Herald TranscriptFeb 17 2017, 4:35 PM

arsenm added a parent revision: D30125: AMDGPU: Merge initial gfx9 support.Feb 17 2017, 4:35 PM

LGTM, thanks.

This revision is now accepted and ready to land.Feb 18 2017, 5:25 AM

r295555

Revision Contents

Path

Size

lib/

Target/

AMDGPU/

Disassembler/

AMDGPUDisassembler.cpp

5 lines

test/

MC/

Disassembler/

AMDGPU/

aperture-regs.ll

13 lines

Diff 88992

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Show First 20 Lines • Show All 517 Lines • ▼ Show 20 Lines	MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
case 107: return createRegOperand(VCC_HI);		case 107: return createRegOperand(VCC_HI);
case 108: return createRegOperand(TBA_LO);		case 108: return createRegOperand(TBA_LO);
case 109: return createRegOperand(TBA_HI);		case 109: return createRegOperand(TBA_HI);
case 110: return createRegOperand(TMA_LO);		case 110: return createRegOperand(TMA_LO);
case 111: return createRegOperand(TMA_HI);		case 111: return createRegOperand(TMA_HI);
case 124: return createRegOperand(M0);		case 124: return createRegOperand(M0);
case 126: return createRegOperand(EXEC_LO);		case 126: return createRegOperand(EXEC_LO);
case 127: return createRegOperand(EXEC_HI);		case 127: return createRegOperand(EXEC_HI);
		case 235: return createRegOperand(SRC_SHARED_BASE);
		case 236: return createRegOperand(SRC_SHARED_LIMIT);
		case 237: return createRegOperand(SRC_PRIVATE_BASE);
		case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
		// TODO: SRC_POPS_EXITING_WAVE_ID
// ToDo: no support for vccz register		// ToDo: no support for vccz register
case 251: break;		case 251: break;
// ToDo: no support for execz register		// ToDo: no support for execz register
case 252: break;		case 252: break;
case 253: return createRegOperand(SCC);		case 253: return createRegOperand(SCC);
default: break;		default: break;
}		}
return errOperand(Val, "unknown operand encoding " + Twine(Val));		return errOperand(Val, "unknown operand encoding " + Twine(Val));
▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines

test/MC/Disassembler/AMDGPU/aperture-regs.ll

This file was added.

				# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s \| FileCheck -check-prefix=GFX9 %s

				# GFX9: v_mov_b32_e32 v1, src_shared_base ; encoding: [0xeb,0x02,0x02,0x7e]
				0xeb 0x02 0x02 0x7e

				# GFX9: v_mov_b32_e32 v1, src_shared_limit ; encoding: [0xec,0x02,0x02,0x7e]
				0xec 0x02 0x02 0x7e

				# GFX9: v_mov_b32_e32 v1, src_private_base ; encoding: [0xed,0x02,0x02,0x7e]
				0xed 0x02 0x02 0x7e

				# GFX9: v_mov_b32_e32 v1, src_private_limit ; encoding: [0xee,0x02,0x02,0x7e]
				0xee 0x02 0x02 0x7e