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[ARM] Fix incorrect mask bits in MSR encoding for write_register intrinsic
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Authored by john.brawn on Feb 10 2017, 7:57 AM.

Details

Summary

In the encoding of system registers in the M-class MSR instruction the mask bits should be 2 for registers that don't take a _<bits> qualifier (the instruction is unpredictable otherwise), and should also be 2 if the register takes a _<bits> qualifier but it's not present as no _<bits> is an alias for _nzcvq.

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Repository
rL LLVM

Event Timeline

john.brawn created this revision.Feb 10 2017, 7:57 AM
rengolin added inline comments.Feb 10 2017, 8:26 AM
test/CodeGen/ARM/special-reg-mcore.ll
26

If you're looking for the encoding bytes, you should use --show-encoding on llvm-mc instead of objdump.

john.brawn added inline comments.Feb 10 2017, 8:43 AM
test/CodeGen/ARM/special-reg-mcore.ll
26

Using llvm-mc means going through assembly, and the bug disappears if you do that (the asm parser gets the encoding of these registers right). It looks like llc has a --show-mc-encoding option though so I'll use that.

john.brawn updated this revision to Diff 88008.Feb 10 2017, 9:00 AM

Use --show-mc-encoding instead of generating an object then disassembling.

rengolin accepted this revision.Feb 10 2017, 9:37 AM

LGTM. Thanks!

This revision is now accepted and ready to land.Feb 10 2017, 9:37 AM
This revision was automatically updated to reflect the committed changes.