[DAGCombiner] (addc X, (adde Y, 0, Carry)) -> (adde X, Y, Carry) when Y + 1 cannot overflow.

[deadalnix]

Summary

This is extracted from D29443 .

[RKSimon]

Should this wait for D29524 and then use SelectionDAG::computeOverflowKind?

[deadalnix]

They can be done in any order. It indeed exposes more combine opportunity with D29524 .

[deadalnix]

Rebase and use computeOverflowKind

[RKSimon]

I take it this needs to wait until we have an answer to the PowerPC DAG issue?

[deadalnix]

This will cause the same problem if X is dependent on the result of the result of the Carry producer in some manner, so yes.

[deadalnix]

This is not relevent anymore.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (LHSZero.getBoolValue()) {
     // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
     // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
     if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
       return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
                        DAG.getNode(ISD::CARRY_FALSE,
                                    SDLoc(N), MVT::Glue));
   }
 
+  // (addc X, (adde Y, 0, Carry)) -> (adde X, Y, Carry)
+  // if Y + 1 cannot overflow.
+  if (N1.getOpcode() == ISD::ADDE &&
+      N1->hasOneUse() &&
+      isNullConstant(N1.getOperand(1))) {
+    APInt YZero, YOne;
+    DAG.computeKnownBits(N1.getOperand(0), YZero, YOne);
+    if (YZero.getBoolValue())
+      return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(), N0,
+                         N1->getOperand(0), N1->getOperand(2));
+  }
+
   return SDValue();
 }
 
 SDValue DAGCombiner::visitADDE(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   SDValue CarryIn = N->getOperand(2);
 

test/CodeGen/X86/adde-carry.ll

  ret void
 }
 
 %scalar = type { [4 x i64] }
 
 define %scalar @pr31719(%scalar* nocapture readonly %this, %scalar %arg.b) {
 ; CHECK-LABEL: pr31719:
 ; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addq (%rsi), %rdx
+; CHECK-NEXT:    addq 8(%rsi), %rcx
 ; CHECK-NEXT:    sbbq %r10, %r10
 ; CHECK-NEXT:    andl $1, %r10d
-; CHECK-NEXT:    addq 8(%rsi), %rcx
-; CHECK-NEXT:    sbbq %r11, %r11
-; CHECK-NEXT:    andl $1, %r11d
-; CHECK-NEXT:    addq %r10, %rcx
-; CHECK-NEXT:    adcq $0, %r11
 ; CHECK-NEXT:    addq 16(%rsi), %r8
 ; CHECK-NEXT:    sbbq %rax, %rax
 ; CHECK-NEXT:    andl $1, %eax
-; CHECK-NEXT:    addq %r11, %r8
+; CHECK-NEXT:    addq (%rsi), %rdx
+; CHECK-NEXT:    adcq $0, %rcx
+; CHECK-NEXT:    adcq %r8, %r10
 ; CHECK-NEXT:    adcq $0, %rax
 ; CHECK-NEXT:    addq 24(%rsi), %r9
 ; CHECK-NEXT:    addq %rax, %r9
 ; CHECK-NEXT:    movq %rdx, (%rdi)
 ; CHECK-NEXT:    movq %rcx, 8(%rdi)
-; CHECK-NEXT:    movq %r8, 16(%rdi)
+; CHECK-NEXT:    movq %r10, 16(%rdi)
 ; CHECK-NEXT:    movq %r9, 24(%rdi)
 ; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %0 = extractvalue %scalar %arg.b, 0
   %.elt = extractvalue [4 x i64] %0, 0
   %.elt24 = extractvalue [4 x i64] %0, 1
   %.elt26 = extractvalue [4 x i64] %0, 2