[PowerPC][Altivec] Add mfvrd and mffprd extended mnemonic

[nemanjai]

Summary

mfvrd and mffprd are both alias to mfvrsd.
This patch enables correct parsing of the aliases, but we still emit a mfvrsd.

Patch by nemanjai

[hfinkel]

Please add a test case so I can see what's going on.

[brunoalr]

In D29177#657519, @hfinkel wrote:

Please add a test case so I can see what's going on.

@nemanjai can you help me with that?

[brunoalr]

In D29177#657519, @hfinkel wrote:

Please add a test case so I can see what's going on.

In D29177#657524, @brunoalr wrote:

In D29177#657519, @hfinkel wrote:

Please add a test case so I can see what's going on.

@nemanjai can you help me with that?

I have a small test case written in C that is just a one-line asm statement, which currently yields an "unrecognized instruction mnemonic" error:

asm ("mfvrd 3, 10\n\t");

, but I lack the knowledge to convert it down to .ll .

[nemanjai]

In D29177#657519, @hfinkel wrote:

Please add a test case so I can see what's going on.

Here's an example of what this will do now (as opposed to emitting the error that Bruno posted):

$ printf "mfvsrd 4, 34\nmfvrd 4, 2" | llvm-mc --show-encoding
      .text
      mfvsrd 4, 34                    # encoding: [0x67,0x00,0x44,0x7c]
      mfvsrd 4, 34                    # encoding: [0x67,0x00,0x44,0x7c]

[hfinkel]

In D29177#657584, @nemanjai wrote:

In D29177#657519, @hfinkel wrote:

Please add a test case so I can see what's going on.

Here's an example of what this will do now (as opposed to emitting the error that Bruno posted):

$ printf "mfvsrd 4, 34\nmfvrd 4, 2" | llvm-mc --show-encoding
      .text
      mfvsrd 4, 34                    # encoding: [0x67,0x00,0x44,0x7c]
      mfvsrd 4, 34                    # encoding: [0x67,0x00,0x44,0x7c]

Seems reasonable to me.

[brunoalr]

We are looking into the most adequate way of including these alias. But we still need extended mnemonics for the lower half of the VSX regs as well.

[nemanjai]

Sorry Bruno, it appears that I can only update this revision if I commandeer it.

[nemanjai]

Provide both of the extended mnemonics for MFVSRD and add/update tests for them.

Please note that changes to test case p8-scalar_vector_conversions.ll may seem unrelated, but the unoptimized IR (no mem2reg) produces different mnemonics in some cases and not others (i.e. depending on which source register is selected). This update just locks the parameter registers to what the calling convention says and thereby fixes the mnemonic choice.

[brunoalr]

In D29177#662701, @nemanjai wrote:

Sorry Bruno, it appears that I can only update this revision if I commandeer it.

No problem! It was you who wrote this patch after all :P
I updated the rev text to include mffprd as well.

[brunoalr]

In D29177#662704, @nemanjai wrote:

Provide both of the extended mnemonics for MFVSRD and add/update tests for them.

Please note that changes to test case p8-scalar_vector_conversions.ll may seem unrelated, but the unoptimized IR (no mem2reg) produces different mnemonics in some cases and not others (i.e. depending on which source register is selected). This update just locks the parameter registers to what the calling convention says and thereby fixes the mnemonic choice.

Hi there, @nemanjai!
Is there any other action that I should take for this patch to get approved?

Thanks.

[nemanjai]

Hi there, @nemanjai!
Is there any other action that I should take for this patch to get approved?

Thanks.

@hfinkel @kbarton Can you guys have a look so we can get this committed?

[hfinkel]

LGTM

[brunoalr]

In D29177#699675, @nemanjai wrote:

Hi there, @nemanjai!
Is there any other action that I should take for this patch to get approved?

Thanks.

@hfinkel @kbarton Can you guys have a look so we can get this committed?

thanks, @nemanjai, @hfinkel !

lib/Target/PowerPC/PPCInstrVSX.td

 
 let UseVSXReg = 1, AddedComplexity = 400 in {
 let Predicates = [HasDirectMove] in {
   // VSX direct move instructions
   def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
                               "mfvsrd $rA, $XT", IIC_VecGeneral,
                               [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
       Requires<[In64BitMode]>;
+  let isCodeGenOnly = 1 in
+  def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vrrc:$XT),
+                             "mfvsrd $rA, $XT", IIC_VecGeneral,
+                             []>,
+      Requires<[In64BitMode]>;
   def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
                                "mfvsrwz $rA, $XT", IIC_VecGeneral,
                                [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
   def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
                               "mtvsrd $XT, $rA", IIC_VecGeneral,
                               [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
       Requires<[In64BitMode]>;
   def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
let Predicates = [IsISA3_0, HasDirectMove] in {
 
   def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT),
                               "mfvsrld $rA, $XT", IIC_VecGeneral,
                               []>, Requires<[In64BitMode]>;
 
 } // IsISA3_0, HasDirectMove
 } // UseVSXReg = 1
 
+// We want to parse this from asm, but we don't want to emit this as it would
+// be emitted with a VSX reg. So leave Emit = 0 here.
+def : InstAlias<"mfvrd $rA, $XT",
+                (MFVRD g8rc:$rA, vrrc:$XT), 0>;
+def : InstAlias<"mffprd $rA, $src",
+                (MFVSRD g8rc:$rA, f8rc:$src)>;
+
 /*  Direct moves of various widths from GPR's into VSR's. Each move lines
     the value up into element 0 (both BE and LE). Namely, entities smaller than
     a doubleword are shifted left and moved for BE. For LE, they're moved, then
     swapped to go into the least significant element of the VSR.
 */
 def MovesToVSR {
   dag BE_BYTE_0 =
     (MTVSRD

test/CodeGen/PowerPC/bitcasts-direct-move.ll

 }
 
 define i64 @f64toi64(double %a) {
 entry:
   %0 = bitcast double %a to i64
   ret i64 %0
 ; CHECK-P7: stxsdx 1,
 ; CHECK-P7: ld 3,
-; CHECK: mfvsrd 3, 1
+; CHECK: mffprd 3, 1
 }
 
 define float @i32tof32(i32 signext %a) {
 entry:
   %0 = bitcast i32 %a to float
   ret float %0
 ; CHECK-P7: stw 3,
 ; CHECK-P7: lfs 1,

 }
 
 define i64 @f64toi64u(double %a) {
 entry:
   %0 = bitcast double %a to i64
   ret i64 %0
 ; CHECK-P7: stxsdx 1,
 ; CHECK-P7: ld 3,
-; CHECK: mfvsrd 3, 1
+; CHECK: mffprd 3, 1
 }
 
 define float @i32utof32(i32 zeroext %a) {
 entry:
   %0 = bitcast i32 %a to float
   ret float %0
 ; CHECK-P7: stw 3,
 ; CHECK-P7: lfs 1,

test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll

 entry:
   %arg.addr = alloca float, align 4
   store float %arg, float* %arg.addr, align 4
   %0 = load float, float* %arg.addr, align 4
   %conv = fptosi float %0 to i64
   ret i64 %conv
 ; CHECK-LABEL: @_Z7testllff
 ; CHECK: xscvdpsxds [[CONVREG13:[0-9]+]], 1
-; CHECK: mfvsrd 3, [[CONVREG13]]
+; CHECK: mffprd 3, [[CONVREG13]]
 }
 
 ; Function Attrs: nounwind
 define float @_Z7testfllx(i64 %arg) {
 entry:
   %arg.addr = alloca i64, align 8
   store i64 %arg, i64* %arg.addr, align 8
   %0 = load i64, i64* %arg.addr, align 8

 entry:
   %arg.addr = alloca double, align 8
   store double %arg, double* %arg.addr, align 8
   %0 = load double, double* %arg.addr, align 8
   %conv = fptosi double %0 to i64
   ret i64 %conv
 ; CHECK-LABEL: @_Z7testlldd
 ; CHECK: xscvdpsxds [[CONVREG14:[0-9]+]], 1
-; CHECK: mfvsrd 3, [[CONVREG14]]
+; CHECK: mffprd 3, [[CONVREG14]]
 }
 
 ; Function Attrs: nounwind
 define double @_Z7testdllx(i64 %arg) {
 entry:
   %arg.addr = alloca i64, align 8
   store i64 %arg, i64* %arg.addr, align 8
   %0 = load i64, i64* %arg.addr, align 8

 entry:
   %arg.addr = alloca float, align 4
   store float %arg, float* %arg.addr, align 4
   %0 = load float, float* %arg.addr, align 4
   %conv = fptoui float %0 to i64
   ret i64 %conv
 ; CHECK-LABEL: @_Z8testullff
 ; CHECK: xscvdpuxds [[CONVREG15:[0-9]+]], 1
-; CHECK: mfvsrd 3, [[CONVREG15]]
+; CHECK: mffprd 3, [[CONVREG15]]
 }
 
 ; Function Attrs: nounwind
 define float @_Z8testfully(i64 %arg) {
 entry:
   %arg.addr = alloca i64, align 8
   store i64 %arg, i64* %arg.addr, align 8
   %0 = load i64, i64* %arg.addr, align 8

 entry:
   %arg.addr = alloca double, align 8
   store double %arg, double* %arg.addr, align 8
   %0 = load double, double* %arg.addr, align 8
   %conv = fptoui double %0 to i64
   ret i64 %conv
 ; CHECK-LABEL: @_Z8testulldd
 ; CHECK: xscvdpuxds [[CONVREG16:[0-9]+]], 1
-; CHECK: mfvsrd 3, [[CONVREG16]]
+; CHECK: mffprd 3, [[CONVREG16]]
 }
 
 ; Function Attrs: nounwind
 define double @_Z8testdully(i64 %arg) {
 entry:
   %arg.addr = alloca i64, align 8
   store i64 %arg, i64* %arg.addr, align 8
   %0 = load i64, i64* %arg.addr, align 8
   %conv = uitofp i64 %0 to double
   ret double %conv
 ; CHECK-LABEL: @_Z8testdully
 ; CHECK: mtvsrd [[MOVEREG16:[0-9]+]], 3
 ; CHECK: xscvuxddp 1, [[MOVEREG16]]
 }

test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll

 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
 ; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
 ; PPC64: and [[FLIP_BIT:[0-9]+]], [[HI]], [[MASK_REG]]
 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
 ; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]]
 ; PPC64: blr
 
 ; PPC64-P8-LABEL: test_abs:
-; PPC64-P8-DAG: mfvsrd [[LO:[0-9]+]], 2
-; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1
+; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2
+; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
 ; PPC64-P8-DAG: li [[MASK_REG:[0-9]+]], 1
 ; PPC64-P8-DAG: sldi [[SHIFT_REG:[0-9]+]], [[MASK_REG]], 63
 ; PPC64-P8: and [[FLIP_BIT:[0-9]+]], [[HI]], [[SHIFT_REG]]
 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
 ; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]]
 ; PPC64-P8: blr
 
 ; PPC32-DAG: stfd 1, 24(1)

 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
 ; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
 ; PPC64-NOT: BARRIER
 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
 ; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]]
 ; PPC64: blr
 
 ; PPC64-P8-LABEL: test_neg:
-; PPC64-P8-DAG: mfvsrd [[LO:[0-9]+]], 2
-; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1
+; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2
+; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
 ; PPC64-P8-DAG: li [[IMM1:[0-9]+]], 1
 ; PPC64-P8-DAG: sldi [[FLIP_BIT]], [[IMM1]], 63
 ; PPC64-P8-NOT: BARRIER
 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
 ; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]]
 ; PPC64-P8: blr
 
 ; PPC32-DAG: stfd 1, 24(1)

 ; PPC64-NOT: BARRIER
 ; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1)
 ; PPC64-DAG: and [[NEW_HI_TMP:[0-9]+]], [[X_HI]], [[SIGN]]
 ; PPC64-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
 ; PPC64-DAG: xor 4, [[SIGN]], [[CST_LO]]
 ; PPC64: blr
 
 ; PPC64-P8-LABEL: test_copysign:
-; PPC64-P8-DAG: mfvsrd [[X_HI:[0-9]+]], 1
+; PPC64-P8-DAG: mffprd [[X_HI:[0-9]+]], 1
 ; PPC64-P8-DAG: li [[SIGN:[0-9]+]], 1
 ; PPC64-P8-DAG: sldi [[SIGN]], [[SIGN]], 63
 ; PPC64-P8-DAG: li [[HI_TMP:[0-9]+]], 16399
 ; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
 ; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019
 ; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
 ; PPC64-P8-NOT: BARRIER
 ; PPC64-P8-DAG: and [[NEW_HI_TMP:[0-9]+]], [[X_HI]], [[SIGN]]

test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll

 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE
 
 ; The build[csilf] functions simply test the scalar_to_vector handling with
 ; direct moves. This corresponds to the "insertelement" instruction. Subsequent
 ; to this, there will be a splat corresponding to the shufflevector.
 
 @d = common global double 0.000000e+00, align 8
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define <16 x i8> @buildc(i8 zeroext %a) {
 entry:
-  %a.addr = alloca i8, align 1
-  store i8 %a, i8* %a.addr, align 1
-  %0 = load i8, i8* %a.addr, align 1
-  %splat.splatinsert = insertelement <16 x i8> undef, i8 %0, i32 0
+  %splat.splatinsert = insertelement <16 x i8> undef, i8 %a, i32 0
   %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
   ret <16 x i8> %splat.splat
 ; CHECK: sldi [[REG1:[0-9]+]], 3, 56
 ; CHECK: mtvsrd {{[0-9]+}}, [[REG1]]
 ; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3
 ; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]]
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define <8 x i16> @builds(i16 zeroext %a) {
 entry:
-  %a.addr = alloca i16, align 2
-  store i16 %a, i16* %a.addr, align 2
-  %0 = load i16, i16* %a.addr, align 2
-  %splat.splatinsert = insertelement <8 x i16> undef, i16 %0, i32 0
+  %splat.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 0
   %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
   ret <8 x i16> %splat.splat
 ; CHECK: sldi [[REG1:[0-9]+]], 3, 48
 ; CHECK: mtvsrd {{[0-9]+}}, [[REG1]]
 ; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3
 ; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]]
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define <4 x i32> @buildi(i32 zeroext %a) {
 entry:
-  %a.addr = alloca i32, align 4
-  store i32 %a, i32* %a.addr, align 4
-  %0 = load i32, i32* %a.addr, align 4
-  %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
+  %splat.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 0
   %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
   ret <4 x i32> %splat.splat
 ; CHECK: mtvsrwz [[REG1:[0-9]+]], 3
 ; CHECK: xxspltw 34, [[REG1]]
 ; CHECK-LE: mtvsrwz [[REG1:[0-9]+]], 3
 ; CHECK-LE: xxspltw 34, [[REG1]]
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define <2 x i64> @buildl(i64 %a) {
 entry:
-  %a.addr = alloca i64, align 8
-  store i64 %a, i64* %a.addr, align 8
-  %0 = load i64, i64* %a.addr, align 8
-  %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
+  %splat.splatinsert = insertelement <2 x i64> undef, i64 %a, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
 ; CHECK: mtvsrd {{[0-9]+}}, 3
 ; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3
 ; CHECK-LE: xxspltd 34, [[REG1]], 0
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define <4 x float> @buildf(float %a) {
 entry:
-  %a.addr = alloca float, align 4
-  store float %a, float* %a.addr, align 4
-  %0 = load float, float* %a.addr, align 4
-  %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0
+  %splat.splatinsert = insertelement <4 x float> undef, float %a, i32 0
   %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
   ret <4 x float> %splat.splat
 ; CHECK: xscvdpspn [[REG1:[0-9]+]], 1
 ; CHECK: xxspltw 34, [[REG1]]
 ; CHECK-LE: xscvdpspn [[REG1:[0-9]+]], 1
 ; CHECK-LE: xxspltw 34, [[REG1]]
 }
 
 ; The optimization to remove stack operations from PPCDAGToDAGISel::Select
 ; should still trigger for v2f64, producing an lxvdsx.
-; Function Attrs: nounwind
-define <2 x double> @buildd() #0 {
+; Function Attrs: norecurse nounwind readonly
+define <2 x double> @buildd() {
 entry:
   %0 = load double, double* @d, align 8
   %splat.splatinsert = insertelement <2 x double> undef, double %0, i32 0
   %splat.splat = shufflevector <2 x double> %splat.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %splat.splat
 ; CHECK: ld [[REG1:[0-9]+]], .LC0@toc@l
 ; CHECK: lxvdsx 34, 0, [[REG1]]
 ; CHECK-LE: ld [[REG1:[0-9]+]], .LC0@toc@l
 ; CHECK-LE: lxvdsx 34, 0, [[REG1]]
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc0(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 0
+  %vecext = extractelement <16 x i8> %vsc, i32 0
   ret i8 %vecext
 ; CHECK-LABEL: @getsc0
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 8, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc0
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: clrldi 3, 3, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc1(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 1
+  %vecext = extractelement <16 x i8> %vsc, i32 1
   ret i8 %vecext
 ; CHECK-LABEL: @getsc1
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 16, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc1
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 56, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc2(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 2
+  %vecext = extractelement <16 x i8> %vsc, i32 2
   ret i8 %vecext
 ; CHECK-LABEL: @getsc2
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 24, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc2
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 48, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc3(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 3
+  %vecext = extractelement <16 x i8> %vsc, i32 3
   ret i8 %vecext
 ; CHECK-LABEL: @getsc3
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 32, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc3
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 40, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc4(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 4
+  %vecext = extractelement <16 x i8> %vsc, i32 4
   ret i8 %vecext
 ; CHECK-LABEL: @getsc4
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 40, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc4
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 32, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc5(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 5
+  %vecext = extractelement <16 x i8> %vsc, i32 5
   ret i8 %vecext
 ; CHECK-LABEL: @getsc5
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 48, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc5
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 24, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc6(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 6
+  %vecext = extractelement <16 x i8> %vsc, i32 6
   ret i8 %vecext
 ; CHECK-LABEL: @getsc6
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 56, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc6
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 16, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc7(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 7
+  %vecext = extractelement <16 x i8> %vsc, i32 7
   ret i8 %vecext
 ; CHECK-LABEL: @getsc7
 ; CHECK: mfvsrd 3, 34
 ; CHECK: clrldi 3, 3, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc7
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 8, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc8(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 8
+  %vecext = extractelement <16 x i8> %vsc, i32 8
   ret i8 %vecext
 ; CHECK-LABEL: @getsc8
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 8, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc8
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: clrldi 3, 3, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc9(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 9
+  %vecext = extractelement <16 x i8> %vsc, i32 9
   ret i8 %vecext
 ; CHECK-LABEL: @getsc9
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 16, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc9
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 56, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc10(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 10
+  %vecext = extractelement <16 x i8> %vsc, i32 10
   ret i8 %vecext
 ; CHECK-LABEL: @getsc10
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 24, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc10
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 48, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc11(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 11
+  %vecext = extractelement <16 x i8> %vsc, i32 11
   ret i8 %vecext
 ; CHECK-LABEL: @getsc11
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 32, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc11
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 40, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc12(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 12
+  %vecext = extractelement <16 x i8> %vsc, i32 12
   ret i8 %vecext
 ; CHECK-LABEL: @getsc12
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 40, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc12
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 32, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc13(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 13
+  %vecext = extractelement <16 x i8> %vsc, i32 13
   ret i8 %vecext
 ; CHECK-LABEL: @getsc13
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 48, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc13
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 24, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc14(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 14
+  %vecext = extractelement <16 x i8> %vsc, i32 14
   ret i8 %vecext
 ; CHECK-LABEL: @getsc14
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 56, 56
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc14
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 16, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc15(<16 x i8> %vsc) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 15
+  %vecext = extractelement <16 x i8> %vsc, i32 15
   ret i8 %vecext
 ; CHECK-LABEL: @getsc15
 ; CHECK: mfvsrd 3,
 ; CHECK: extsb 3, 3
 ; CHECK-LE-LABEL: @getsc15
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 8, 56
 ; CHECK-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc0(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 0
+  %vecext = extractelement <16 x i8> %vuc, i32 0
   ret i8 %vecext
 ; CHECK-LABEL: @getuc0
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 8, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc0
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc1(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 1
+  %vecext = extractelement <16 x i8> %vuc, i32 1
   ret i8 %vecext
 ; CHECK-LABEL: @getuc1
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 16, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc1
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 56, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc2(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 2
+  %vecext = extractelement <16 x i8> %vuc, i32 2
   ret i8 %vecext
 ; CHECK-LABEL: @getuc2
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 24, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc2
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 48, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc3(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 3
+  %vecext = extractelement <16 x i8> %vuc, i32 3
   ret i8 %vecext
 ; CHECK-LABEL: @getuc3
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 32, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc3
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 40, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc4(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 4
+  %vecext = extractelement <16 x i8> %vuc, i32 4
   ret i8 %vecext
 ; CHECK-LABEL: @getuc4
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 40, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc4
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 32, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc5(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 5
+  %vecext = extractelement <16 x i8> %vuc, i32 5
   ret i8 %vecext
 ; CHECK-LABEL: @getuc5
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 48, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc5
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 24, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc6(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 6
+  %vecext = extractelement <16 x i8> %vuc, i32 6
   ret i8 %vecext
 ; CHECK-LABEL: @getuc6
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 56, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc6
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 16, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc7(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 7
+  %vecext = extractelement <16 x i8> %vuc, i32 7
   ret i8 %vecext
 ; CHECK-LABEL: @getuc7
 ; CHECK: mfvsrd 3, 34
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc7
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 8, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc8(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 8
+  %vecext = extractelement <16 x i8> %vuc, i32 8
   ret i8 %vecext
 ; CHECK-LABEL: @getuc8
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 8, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc8
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc9(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 9
+  %vecext = extractelement <16 x i8> %vuc, i32 9
   ret i8 %vecext
 ; CHECK-LABEL: @getuc9
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 16, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc9
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 56, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc10(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 10
+  %vecext = extractelement <16 x i8> %vuc, i32 10
   ret i8 %vecext
 ; CHECK-LABEL: @getuc10
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 24, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc10
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 48, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc11(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 11
+  %vecext = extractelement <16 x i8> %vuc, i32 11
   ret i8 %vecext
 ; CHECK-LABEL: @getuc11
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 32, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc11
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 40, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc12(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 12
+  %vecext = extractelement <16 x i8> %vuc, i32 12
   ret i8 %vecext
 ; CHECK-LABEL: @getuc12
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 40, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc12
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 32, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc13(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 13
+  %vecext = extractelement <16 x i8> %vuc, i32 13
   ret i8 %vecext
 ; CHECK-LABEL: @getuc13
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 48, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc13
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 24, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc14(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 14
+  %vecext = extractelement <16 x i8> %vuc, i32 14
   ret i8 %vecext
 ; CHECK-LABEL: @getuc14
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 56, 56
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc14
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 16, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc15(<16 x i8> %vuc) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %vecext = extractelement <16 x i8> %0, i32 15
+  %vecext = extractelement <16 x i8> %vuc, i32 15
   ret i8 %vecext
 ; CHECK-LABEL: @getuc15
 ; CHECK: mfvsrd 3,
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc15
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 8, 56
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) {
 entry:
-  %vsc.addr = alloca <16 x i8>, align 16
-  %i.addr = alloca i32, align 4
-  store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
-  store i32 %i, i32* %i.addr, align 4
-  %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
-  %1 = load i32, i32* %i.addr, align 4
-  %vecext = extractelement <16 x i8> %0, i32 %1
+  %vecext = extractelement <16 x i8> %vsc, i32 %i
   ret i8 %vecext
 ; CHECK-LABEL: @getvelsc
 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8
 ; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]]
 ; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
 ; CHECK-DAG: mfvsrd [[MOV:[0-9]+]],
 ; CHECK-DAG: li [[IMM7:[0-9]+]], 7
 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]]
 ; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3
 ; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
 ; CHECK-DAG: extsb 3, 3
 ; CHECK-LE-LABEL: @getvelsc
 ; CHECK-DAG-LE: li [[IMM8:[0-9]+]], 8
 ; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]]
 ; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[ANDC]]
 ; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
 ; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]],
 ; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7
 ; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]]
 ; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3
 ; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
 ; CHECK-DAG-LE: extsb 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getveluc(<16 x i8> %vuc, i32 signext %i) {
 entry:
-  %vuc.addr = alloca <16 x i8>, align 16
-  %i.addr = alloca i32, align 4
-  store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
-  store i32 %i, i32* %i.addr, align 4
-  %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
-  %1 = load i32, i32* %i.addr, align 4
-  %vecext = extractelement <16 x i8> %0, i32 %1
+  %vecext = extractelement <16 x i8> %vuc, i32 %i
   ret i8 %vecext
 ; CHECK-LABEL: @getveluc
 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8
 ; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]]
 ; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
 ; CHECK-DAG: mfvsrd [[MOV:[0-9]+]],
 ; CHECK-DAG: li [[IMM7:[0-9]+]], 7
 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]]
 ; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3
 ; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
 ; CHECK-DAG: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getveluc
 ; CHECK-DAG-LE: li [[IMM8:[0-9]+]], 8
 ; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]]
 ; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[ANDC]]
 ; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
 ; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]],
 ; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7
 ; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]]
 ; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3
 ; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
 ; CHECK-DAG-LE: clrldi   3, 3, 56
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss0(<8 x i16> %vss) {
 entry:
-  %vss.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 0
+  %vecext = extractelement <8 x i16> %vss, i32 0
   ret i16 %vecext
 ; CHECK-LABEL: @getss0
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 16, 48
 ; CHECK: extsh 3, 3
 ; CHECK-LE-LABEL: @getss0
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: clrldi 3, 3, 48
 ; CHECK-LE: extsh 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss1(<8 x i16> %vss) {
 entry:
-  %vss.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 1
+  %vecext = extractelement <8 x i16> %vss, i32 1
   ret i16 %vecext
 ; CHECK-LABEL: @getss1
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 32, 48
 ; CHECK: extsh 3, 3
 ; CHECK-LE-LABEL: @getss1
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 48, 48
 ; CHECK-LE: extsh 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss2(<8 x i16> %vss) {
 entry:
-  %vss.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 2
+  %vecext = extractelement <8 x i16> %vss, i32 2
   ret i16 %vecext
 ; CHECK-LABEL: @getss2
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 48, 48
 ; CHECK: extsh 3, 3
 ; CHECK-LE-LABEL: @getss2
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 32, 48
 ; CHECK-LE: extsh 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss3(<8 x i16> %vss) {
 entry:
-  %vss.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 3
+  %vecext = extractelement <8 x i16> %vss, i32 3
   ret i16 %vecext
 ; CHECK-LABEL: @getss3
 ; CHECK: mfvsrd 3, 34
 ; CHECK: clrldi 3, 3, 48
 ; CHECK: extsh 3, 3
 ; CHECK-LE-LABEL: @getss3
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 16, 48
 ; CHECK-LE: extsh 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss4(<8 x i16> %vss) {
 entry:
-  %vss.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 4
+  %vecext = extractelement <8 x i16> %vss, i32 4
   ret i16 %vecext
 ; CHECK-LABEL: @getss4
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 16, 48
 ; CHECK: extsh 3, 3
 ; CHECK-LE-LABEL: @getss4
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: clrldi 3, 3, 48
 ; CHECK-LE: extsh 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss5(<8 x i16> %vss) {
 entry:
-  %vss.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 5
+  %vecext = extractelement <8 x i16> %vss, i32 5
   ret i16 %vecext
 ; CHECK-LABEL: @getss5
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 32, 48
 ; CHECK: extsh 3, 3
 ; CHECK-LE-LABEL: @getss5
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 48, 48
 ; CHECK-LE: extsh 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss6(<8 x i16> %vss) {
 entry:
-  %vss.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 6
+  %vecext = extractelement <8 x i16> %vss, i32 6
   ret i16 %vecext
 ; CHECK-LABEL: @getss6
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 48, 48
 ; CHECK: extsh 3, 3
 ; CHECK-LE-LABEL: @getss6
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 32, 48
 ; CHECK-LE: extsh 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss7(<8 x i16> %vss) {
 entry:
-  %vss.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 7
+  %vecext = extractelement <8 x i16> %vss, i32 7
   ret i16 %vecext
 ; CHECK-LABEL: @getss7
 ; CHECK: mfvsrd 3,
 ; CHECK: extsh 3, 3
 ; CHECK-LE-LABEL: @getss7
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 16, 48
 ; CHECK-LE: extsh 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus0(<8 x i16> %vus) {
 entry:
-  %vus.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 0
+  %vecext = extractelement <8 x i16> %vus, i32 0
   ret i16 %vecext
 ; CHECK-LABEL: @getus0
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 16, 48
 ; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus0
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: clrldi   3, 3, 48
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus1(<8 x i16> %vus) {
 entry:
-  %vus.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 1
+  %vecext = extractelement <8 x i16> %vus, i32 1
   ret i16 %vecext
 ; CHECK-LABEL: @getus1
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 32, 48
 ; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus1
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 48, 48
 ; CHECK-LE: clrldi   3, 3, 48
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus2(<8 x i16> %vus) {
 entry:
-  %vus.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 2
+  %vecext = extractelement <8 x i16> %vus, i32 2
   ret i16 %vecext
 ; CHECK-LABEL: @getus2
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 48, 48
 ; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus2
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 32, 48
 ; CHECK-LE: clrldi   3, 3, 48
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus3(<8 x i16> %vus) {
 entry:
-  %vus.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 3
+  %vecext = extractelement <8 x i16> %vus, i32 3
   ret i16 %vecext
 ; CHECK-LABEL: @getus3
 ; CHECK: mfvsrd 3, 34
 ; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus3
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 16, 48
 ; CHECK-LE: clrldi   3, 3, 48
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus4(<8 x i16> %vus) {
 entry:
-  %vus.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 4
+  %vecext = extractelement <8 x i16> %vus, i32 4
   ret i16 %vecext
 ; CHECK-LABEL: @getus4
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 16, 48
 ; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus4
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: clrldi   3, 3, 48
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus5(<8 x i16> %vus) {
 entry:
-  %vus.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 5
+  %vecext = extractelement <8 x i16> %vus, i32 5
   ret i16 %vecext
 ; CHECK-LABEL: @getus5
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 32, 48
 ; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus5
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 48, 48
 ; CHECK-LE: clrldi   3, 3, 48
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus6(<8 x i16> %vus) {
 entry:
-  %vus.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 6
+  %vecext = extractelement <8 x i16> %vus, i32 6
   ret i16 %vecext
 ; CHECK-LABEL: @getus6
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 48, 48
 ; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus6
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 32, 48
 ; CHECK-LE: clrldi   3, 3, 48
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus7(<8 x i16> %vus) {
 entry:
-  %vus.addr = alloca <8 x i16>, align 16
-  store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
-  %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
-  %vecext = extractelement <8 x i16> %0, i32 7
+  %vecext = extractelement <8 x i16> %vus, i32 7
   ret i16 %vecext
 ; CHECK-LABEL: @getus7
 ; CHECK: mfvsrd 3,
 ; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus7
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 16, 48
 ; CHECK-LE: clrldi   3, 3, 48
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) {
 entry:
-  %vss.addr = alloca <8 x i16>, align 16
-  %i.addr = alloca i32, align 4
-  store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
-  store i32 %i, i32* %i.addr, align 4
-  %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
-  %1 = load i32, i32* %i.addr, align 4
-  %vecext = extractelement <8 x i16> %0, i32 %1
+  %vecext = extractelement <8 x i16> %vss, i32 %i
   ret i16 %vecext
 ; CHECK-LABEL: @getvelss
 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4
 ; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1
 ; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]]
 ; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
 ; CHECK-DAG: mfvsrd [[MOV:[0-9]+]],
 ; CHECK-DAG: li [[IMM3:[0-9]+]], 3

 ; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]],
 ; CHECK-DAG-LE: li [[IMM3:[0-9]+]], 3
 ; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM3]]
 ; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 4
 ; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
 ; CHECK-DAG-LE: extsh 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getvelus(<8 x i16> %vus, i32 signext %i) {
 entry:
-  %vus.addr = alloca <8 x i16>, align 16
-  %i.addr = alloca i32, align 4
-  store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
-  store i32 %i, i32* %i.addr, align 4
-  %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
-  %1 = load i32, i32* %i.addr, align 4
-  %vecext = extractelement <8 x i16> %0, i32 %1
+  %vecext = extractelement <8 x i16> %vus, i32 %i
   ret i16 %vecext
 ; CHECK-LABEL: @getvelus
 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4
 ; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1
 ; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]]
 ; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]]
 ; CHECK-DAG: mfvsrd [[MOV:[0-9]+]],
 ; CHECK-DAG: li [[IMM3:[0-9]+]], 3

 ; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]],
 ; CHECK-DAG-LE: li [[IMM3:[0-9]+]], 3
 ; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM3]]
 ; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 4
 ; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
 ; CHECK-DAG-LE: clrldi   3, 3, 48
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i32 @getsi0(<4 x i32> %vsi) {
 entry:
-  %vsi.addr = alloca <4 x i32>, align 16
-  store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16
-  %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16
-  %vecext = extractelement <4 x i32> %0, i32 0
+  %vecext = extractelement <4 x i32> %vsi, i32 0
   ret i32 %vecext
 ; CHECK-LABEL: @getsi0
 ; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
 ; CHECK: mfvsrwz 3, [[SHL]]
 ; CHECK: extsw 3, 3
 ; CHECK-LE-LABEL: @getsi0
 ; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK-LE: mfvsrwz 3, [[SHL]]
 ; CHECK-LE: extsw 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i32 @getsi1(<4 x i32> %vsi) {
 entry:
-  %vsi.addr = alloca <4 x i32>, align 16
-  store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16
-  %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16
-  %vecext = extractelement <4 x i32> %0, i32 1
+  %vecext = extractelement <4 x i32> %vsi, i32 1
   ret i32 %vecext
 ; CHECK-LABEL: @getsi1
 ; CHECK: mfvsrwz 3, 34
 ; CHECK: extsw 3, 3
 ; CHECK-LE-LABEL: @getsi1
 ; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
 ; CHECK-LE: mfvsrwz 3, [[SHL]]
 ; CHECK-LE: extsw 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i32 @getsi2(<4 x i32> %vsi) {
 entry:
-  %vsi.addr = alloca <4 x i32>, align 16
-  store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16
-  %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16
-  %vecext = extractelement <4 x i32> %0, i32 2
+  %vecext = extractelement <4 x i32> %vsi, i32 2
   ret i32 %vecext
 ; CHECK-LABEL: @getsi2
 ; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
 ; CHECK: mfvsrwz 3, [[SHL]]
 ; CHECK: extsw 3, 3
 ; CHECK-LE-LABEL: @getsi2
 ; CHECK-LE: mfvsrwz 3, 34
 ; CHECK-LE: extsw 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i32 @getsi3(<4 x i32> %vsi) {
 entry:
-  %vsi.addr = alloca <4 x i32>, align 16
-  store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16
-  %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16
-  %vecext = extractelement <4 x i32> %0, i32 3
+  %vecext = extractelement <4 x i32> %vsi, i32 3
   ret i32 %vecext
 ; CHECK-LABEL: @getsi3
 ; CHECK: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK: mfvsrwz 3, [[SHL]]
 ; CHECK: extsw 3, 3
 ; CHECK-LE-LABEL: @getsi3
 ; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
 ; CHECK-LE: mfvsrwz 3, [[SHL]]
 ; CHECK-LE: extsw 3, 3
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui0(<4 x i32> %vui) {
 entry:
-  %vui.addr = alloca <4 x i32>, align 16
-  store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16
-  %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16
-  %vecext = extractelement <4 x i32> %0, i32 0
+  %vecext = extractelement <4 x i32> %vui, i32 0
   ret i32 %vecext
 ; CHECK-LABEL: @getui0
 ; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
 ; CHECK: mfvsrwz 3, [[SHL]]
 ; CHECK: clrldi   3, 3, 32
 ; CHECK-LE-LABEL: @getui0
 ; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK-LE: mfvsrwz 3, [[SHL]]
 ; CHECK-LE: clrldi   3, 3, 32
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui1(<4 x i32> %vui) {
 entry:
-  %vui.addr = alloca <4 x i32>, align 16
-  store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16
-  %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16
-  %vecext = extractelement <4 x i32> %0, i32 1
+  %vecext = extractelement <4 x i32> %vui, i32 1
   ret i32 %vecext
 ; CHECK-LABEL: @getui1
 ; CHECK: mfvsrwz 3, 34
 ; CHECK: clrldi   3, 3, 32
 ; CHECK-LE-LABEL: @getui1
 ; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
 ; CHECK-LE: mfvsrwz 3, [[SHL]]
 ; CHECK-LE: clrldi   3, 3, 32
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui2(<4 x i32> %vui) {
 entry:
-  %vui.addr = alloca <4 x i32>, align 16
-  store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16
-  %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16
-  %vecext = extractelement <4 x i32> %0, i32 2
+  %vecext = extractelement <4 x i32> %vui, i32 2
   ret i32 %vecext
 ; CHECK-LABEL: @getui2
 ; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
 ; CHECK: mfvsrwz 3, [[SHL]]
 ; CHECK: clrldi   3, 3, 32
 ; CHECK-LE-LABEL: @getui2
 ; CHECK-LE: mfvsrwz 3, 34
 ; CHECK-LE: clrldi   3, 3, 32
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui3(<4 x i32> %vui) {
 entry:
-  %vui.addr = alloca <4 x i32>, align 16
-  store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16
-  %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16
-  %vecext = extractelement <4 x i32> %0, i32 3
+  %vecext = extractelement <4 x i32> %vui, i32 3
   ret i32 %vecext
 ; CHECK-LABEL: @getui3
 ; CHECK: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK: mfvsrwz 3, [[SHL]]
 ; CHECK: clrldi   3, 3, 32
 ; CHECK-LE-LABEL: @getui3
 ; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
 ; CHECK-LE: mfvsrwz 3, [[SHL]]
 ; CHECK-LE: clrldi   3, 3, 32
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) {
 entry:
-  %vsi.addr = alloca <4 x i32>, align 16
-  %i.addr = alloca i32, align 4
-  store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16
-  store i32 %i, i32* %i.addr, align 4
-  %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16
-  %1 = load i32, i32* %i.addr, align 4
-  %vecext = extractelement <4 x i32> %0, i32 %1
+  %vecext = extractelement <4 x i32> %vsi, i32 %i
   ret i32 %vecext
 ; CHECK-LABEL: @getvelsi
 ; CHECK-LE-LABEL: @getvelsi
 ; FIXME: add check patterns when variable element extraction is implemented
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getvelui(<4 x i32> %vui, i32 signext %i) {
 entry:
-  %vui.addr = alloca <4 x i32>, align 16
-  %i.addr = alloca i32, align 4
-  store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16
-  store i32 %i, i32* %i.addr, align 4
-  %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16
-  %1 = load i32, i32* %i.addr, align 4
-  %vecext = extractelement <4 x i32> %0, i32 %1
+  %vecext = extractelement <4 x i32> %vui, i32 %i
   ret i32 %vecext
 ; CHECK-LABEL: @getvelui
 ; CHECK-LE-LABEL: @getvelui
 ; FIXME: add check patterns when variable element extraction is implemented
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define i64 @getsl0(<2 x i64> %vsl) {
 entry:
-  %vsl.addr = alloca <2 x i64>, align 16
-  store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16
-  %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16
-  %vecext = extractelement <2 x i64> %0, i32 0
+  %vecext = extractelement <2 x i64> %vsl, i32 0
   ret i64 %vecext
 ; CHECK-LABEL: @getsl0
 ; CHECK: mfvsrd 3, 34
 ; CHECK-LE-LABEL: @getsl0
 ; CHECK-LE: xxswapd  [[SWP:[0-9]+]], 34
 ; CHECK-LE: mfvsrd 3, [[SWP]]
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define i64 @getsl1(<2 x i64> %vsl) {
 entry:
-  %vsl.addr = alloca <2 x i64>, align 16
-  store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16
-  %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16
-  %vecext = extractelement <2 x i64> %0, i32 1
+  %vecext = extractelement <2 x i64> %vsl, i32 1
   ret i64 %vecext
 ; CHECK-LABEL: @getsl1
 ; CHECK: xxswapd  [[SWP:[0-9]+]], 34
 ; CHECK: mfvsrd 3, [[SWP]]
 ; CHECK-LE-LABEL: @getsl1
 ; CHECK-LE: mfvsrd 3, 34
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define i64 @getul0(<2 x i64> %vul) {
 entry:
-  %vul.addr = alloca <2 x i64>, align 16
-  store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16
-  %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16
-  %vecext = extractelement <2 x i64> %0, i32 0
+  %vecext = extractelement <2 x i64> %vul, i32 0
   ret i64 %vecext
 ; CHECK-LABEL: @getul0
 ; CHECK: mfvsrd 3, 34
 ; CHECK-LE-LABEL: @getul0
 ; CHECK-LE: xxswapd  [[SWP:[0-9]+]], 34
 ; CHECK-LE: mfvsrd 3, [[SWP]]
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define i64 @getul1(<2 x i64> %vul) {
 entry:
-  %vul.addr = alloca <2 x i64>, align 16
-  store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16
-  %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16
-  %vecext = extractelement <2 x i64> %0, i32 1
+  %vecext = extractelement <2 x i64> %vul, i32 1
   ret i64 %vecext
 ; CHECK-LABEL: @getul1
 ; CHECK: xxswapd  [[SWP:[0-9]+]], 34
 ; CHECK: mfvsrd 3, [[SWP]]
 ; CHECK-LE-LABEL: @getul1
 ; CHECK-LE: mfvsrd 3, 34
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) {
 entry:
-  %vsl.addr = alloca <2 x i64>, align 16
-  %i.addr = alloca i32, align 4
-  store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16
-  store i32 %i, i32* %i.addr, align 4
-  %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16
-  %1 = load i32, i32* %i.addr, align 4
-  %vecext = extractelement <2 x i64> %0, i32 %1
+  %vecext = extractelement <2 x i64> %vsl, i32 %i
   ret i64 %vecext
 ; CHECK-LABEL: @getvelsl
 ; CHECK-LE-LABEL: @getvelsl
 ; FIXME: add check patterns when variable element extraction is implemented
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define i64 @getvelul(<2 x i64> %vul, i32 signext %i) {
 entry:
-  %vul.addr = alloca <2 x i64>, align 16
-  %i.addr = alloca i32, align 4
-  store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16
-  store i32 %i, i32* %i.addr, align 4
-  %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16
-  %1 = load i32, i32* %i.addr, align 4
-  %vecext = extractelement <2 x i64> %0, i32 %1
+  %vecext = extractelement <2 x i64> %vul, i32 %i
   ret i64 %vecext
 ; CHECK-LABEL: @getvelul
 ; CHECK-LE-LABEL: @getvelul
 ; FIXME: add check patterns when variable element extraction is implemented
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define float @getf0(<4 x float> %vf) {
 entry:
-  %vf.addr = alloca <4 x float>, align 16
-  store <4 x float> %vf, <4 x float>* %vf.addr, align 16
-  %0 = load <4 x float>, <4 x float>* %vf.addr, align 16
-  %vecext = extractelement <4 x float> %0, i32 0
+  %vecext = extractelement <4 x float> %vf, i32 0
   ret float %vecext
 ; CHECK-LABEL: @getf0
 ; CHECK: xscvspdpn 1, 34
 ; CHECK-LE-LABEL: @getf0
 ; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
 ; CHECK-LE: xscvspdpn 1, [[SHL]]
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define float @getf1(<4 x float> %vf) {
 entry:
-  %vf.addr = alloca <4 x float>, align 16
-  store <4 x float> %vf, <4 x float>* %vf.addr, align 16
-  %0 = load <4 x float>, <4 x float>* %vf.addr, align 16
-  %vecext = extractelement <4 x float> %0, i32 1
+  %vecext = extractelement <4 x float> %vf, i32 1
   ret float %vecext
 ; CHECK-LABEL: @getf1
 ; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
 ; CHECK: xscvspdpn 1, [[SHL]]
 ; CHECK-LE-LABEL: @getf1
 ; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK-LE: xscvspdpn 1, [[SHL]]
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define float @getf2(<4 x float> %vf) {
 entry:
-  %vf.addr = alloca <4 x float>, align 16
-  store <4 x float> %vf, <4 x float>* %vf.addr, align 16
-  %0 = load <4 x float>, <4 x float>* %vf.addr, align 16
-  %vecext = extractelement <4 x float> %0, i32 2
+  %vecext = extractelement <4 x float> %vf, i32 2
   ret float %vecext
 ; CHECK-LABEL: @getf2
 ; CHECK: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK: xscvspdpn 1, [[SHL]]
 ; CHECK-LE-LABEL: @getf2
 ; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
 ; CHECK-LE: xscvspdpn 1, [[SHL]]
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define float @getf3(<4 x float> %vf) {
 entry:
-  %vf.addr = alloca <4 x float>, align 16
-  store <4 x float> %vf, <4 x float>* %vf.addr, align 16
-  %0 = load <4 x float>, <4 x float>* %vf.addr, align 16
-  %vecext = extractelement <4 x float> %0, i32 3
+  %vecext = extractelement <4 x float> %vf, i32 3
   ret float %vecext
 ; CHECK-LABEL: @getf3
 ; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
 ; CHECK: xscvspdpn 1, [[SHL]]
 ; CHECK-LE-LABEL: @getf3
 ; CHECK-LE: xscvspdpn 1, 34
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define float @getvelf(<4 x float> %vf, i32 signext %i) {
 entry:
-  %vf.addr = alloca <4 x float>, align 16
-  %i.addr = alloca i32, align 4
-  store <4 x float> %vf, <4 x float>* %vf.addr, align 16
-  store i32 %i, i32* %i.addr, align 4
-  %0 = load <4 x float>, <4 x float>* %vf.addr, align 16
-  %1 = load i32, i32* %i.addr, align 4
-  %vecext = extractelement <4 x float> %0, i32 %1
+  %vecext = extractelement <4 x float> %vf, i32 %i
   ret float %vecext
 ; CHECK-LABEL: @getvelf
 ; CHECK-LE-LABEL: @getvelf
 ; FIXME: add check patterns when variable element extraction is implemented
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define double @getd0(<2 x double> %vd) {
 entry:
-  %vd.addr = alloca <2 x double>, align 16
-  store <2 x double> %vd, <2 x double>* %vd.addr, align 16
-  %0 = load <2 x double>, <2 x double>* %vd.addr, align 16
-  %vecext = extractelement <2 x double> %0, i32 0
+  %vecext = extractelement <2 x double> %vd, i32 0
   ret double %vecext
 ; CHECK-LABEL: @getd0
 ; CHECK: xxlor 1, 34, 34
 ; CHECK-LE-LABEL: @getd0
 ; CHECK-LE: xxswapd  1, 34
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define double @getd1(<2 x double> %vd) {
 entry:
-  %vd.addr = alloca <2 x double>, align 16
-  store <2 x double> %vd, <2 x double>* %vd.addr, align 16
-  %0 = load <2 x double>, <2 x double>* %vd.addr, align 16
-  %vecext = extractelement <2 x double> %0, i32 1
+  %vecext = extractelement <2 x double> %vd, i32 1
   ret double %vecext
 ; CHECK-LABEL: @getd1
 ; CHECK: xxswapd  1, 34
 ; CHECK-LE-LABEL: @getd1
 ; CHECK-LE: xxlor 1, 34, 34
 }
 
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
 define double @getveld(<2 x double> %vd, i32 signext %i) {
 entry:
-  %vd.addr = alloca <2 x double>, align 16
-  %i.addr = alloca i32, align 4
-  store <2 x double> %vd, <2 x double>* %vd.addr, align 16
-  store i32 %i, i32* %i.addr, align 4
-  %0 = load <2 x double>, <2 x double>* %vd.addr, align 16
-  %1 = load i32, i32* %i.addr, align 4
-  %vecext = extractelement <2 x double> %0, i32 %1
+  %vecext = extractelement <2 x double> %vd, i32 %i
   ret double %vecext
 ; CHECK-LABEL: @getveld
 ; CHECK-LE-LABEL: @getveld
 ; FIXME: add check patterns when variable element extraction is implemented
 }

test/MC/Disassembler/PowerPC/vsx.txt

 0xf0 0xff 0xfb 0x56
 
 # CHECK: xxspltw 7, 27, 3
 0xf0 0xe3 0xda 0x90
 
 # CHECK: xxswapd 7, 63
 0xf0 0xff 0xfa 0x56
 
-# CHECK: mfvsrd 3, 0
-0x7c 0x03 0x00 0x66
+# CHECK: mfvsrd 3, 40
+0x7d 0x03 0x00 0x67
 
 # CHECK: mfvsrwz 5, 0
 0x7c 0x05 0x00 0xe6
 
 # CHECK: mtvsrd 0, 3
 0x7c 0x03 0x01 0x66
 
 # CHECK: mtvsrwa 0, 3

test/MC/PowerPC/vsx.s

 # CHECK-BE: xxspltw 7, 27, 3                   # encoding: [0xf0,0xe3,0xda,0x90]
 # CHECK-LE: xxspltw 7, 27, 3                   # encoding: [0x90,0xda,0xe3,0xf0]
             xxspltw 7, 27, 3
 # CHECK-BE: xxswapd 7, 63                      # encoding: [0xf0,0xff,0xfa,0x56]
 # CHECK-LE: xxswapd 7, 63                      # encoding: [0x56,0xfa,0xff,0xf0]
             xxswapd 7, 63
 
 # Move to/from VSR
-# CHECK-BE: mfvsrd 3, 0                        # encoding: [0x7c,0x03,0x00,0x66]
-# CHECK-LE: mfvsrd 3, 0                        # encoding: [0x66,0x00,0x03,0x7c]
-            mfvsrd 3, 0
+# CHECK-BE: mfvsrd 3, 40                       # encoding: [0x7d,0x03,0x00,0x67]
+# CHECK-LE: mfvsrd 3, 40                       # encoding: [0x67,0x00,0x03,0x7d]
+            mfvsrd 3, 40
+# CHECK-BE: mfvsrd 3, 40                       # encoding: [0x7d,0x03,0x00,0x67]
+# CHECK-LE: mfvsrd 3, 40                       # encoding: [0x67,0x00,0x03,0x7d]
+            mfvrd 3, 8
 # CHECK-BE: mfvsrwz 5, 0                       # encoding: [0x7c,0x05,0x00,0xe6]
 # CHECK-LE: mfvsrwz 5, 0                       # encoding: [0xe6,0x00,0x05,0x7c]
             mfvsrwz 5, 0
 # CHECK-BE: mtvsrd 0, 3                        # encoding: [0x7c,0x03,0x01,0x66]
 # CHECK-LE: mtvsrd 0, 3                        # encoding: [0x66,0x01,0x03,0x7c]
             mtvsrd 0, 3
 # CHECK-BE: mtvsrwa 0, 3                       # encoding: [0x7c,0x03,0x01,0xa6]
 # CHECK-LE: mtvsrwa 0, 3                       # encoding: [0xa6,0x01,0x03,0x7c]