[PowerPC][Altivec] Add mfvrd and mffprd extended mnemonic

[nemanjai]

Summary

mfvrd and mffprd are both alias to mfvrsd.
This patch enables correct parsing of the aliases, but we still emit a mfvrsd.

Patch by nemanjai

[hfinkel]

Please add a test case so I can see what's going on.

[brunoalr]

In D29177#657519, @hfinkel wrote:

Please add a test case so I can see what's going on.

@nemanjai can you help me with that?

[brunoalr]

In D29177#657519, @hfinkel wrote:

Please add a test case so I can see what's going on.

In D29177#657524, @brunoalr wrote:

In D29177#657519, @hfinkel wrote:

Please add a test case so I can see what's going on.

@nemanjai can you help me with that?

I have a small test case written in C that is just a one-line asm statement, which currently yields an "unrecognized instruction mnemonic" error:

asm ("mfvrd 3, 10\n\t");

, but I lack the knowledge to convert it down to .ll .

[nemanjai]

In D29177#657519, @hfinkel wrote:

Please add a test case so I can see what's going on.

Here's an example of what this will do now (as opposed to emitting the error that Bruno posted):

$ printf "mfvsrd 4, 34\nmfvrd 4, 2" | llvm-mc --show-encoding
      .text
      mfvsrd 4, 34                    # encoding: [0x67,0x00,0x44,0x7c]
      mfvsrd 4, 34                    # encoding: [0x67,0x00,0x44,0x7c]

[hfinkel]

In D29177#657584, @nemanjai wrote:

In D29177#657519, @hfinkel wrote:

Please add a test case so I can see what's going on.

Here's an example of what this will do now (as opposed to emitting the error that Bruno posted):

$ printf "mfvsrd 4, 34\nmfvrd 4, 2" | llvm-mc --show-encoding
      .text
      mfvsrd 4, 34                    # encoding: [0x67,0x00,0x44,0x7c]
      mfvsrd 4, 34                    # encoding: [0x67,0x00,0x44,0x7c]

Seems reasonable to me.

[brunoalr]

We are looking into the most adequate way of including these alias. But we still need extended mnemonics for the lower half of the VSX regs as well.

[nemanjai]

Sorry Bruno, it appears that I can only update this revision if I commandeer it.

[nemanjai]

Provide both of the extended mnemonics for MFVSRD and add/update tests for them.

Please note that changes to test case p8-scalar_vector_conversions.ll may seem unrelated, but the unoptimized IR (no mem2reg) produces different mnemonics in some cases and not others (i.e. depending on which source register is selected). This update just locks the parameter registers to what the calling convention says and thereby fixes the mnemonic choice.

[brunoalr]

In D29177#662701, @nemanjai wrote:

Sorry Bruno, it appears that I can only update this revision if I commandeer it.

No problem! It was you who wrote this patch after all :P
I updated the rev text to include mffprd as well.

[brunoalr]

In D29177#662704, @nemanjai wrote:

Provide both of the extended mnemonics for MFVSRD and add/update tests for them.

Please note that changes to test case p8-scalar_vector_conversions.ll may seem unrelated, but the unoptimized IR (no mem2reg) produces different mnemonics in some cases and not others (i.e. depending on which source register is selected). This update just locks the parameter registers to what the calling convention says and thereby fixes the mnemonic choice.

Hi there, @nemanjai!
Is there any other action that I should take for this patch to get approved?

Thanks.

[nemanjai]

Hi there, @nemanjai!
Is there any other action that I should take for this patch to get approved?

Thanks.

@hfinkel @kbarton Can you guys have a look so we can get this committed?

[hfinkel]

LGTM

[brunoalr]

In D29177#699675, @nemanjai wrote:

Hi there, @nemanjai!
Is there any other action that I should take for this patch to get approved?

Thanks.

@hfinkel @kbarton Can you guys have a look so we can get this committed?

thanks, @nemanjai, @hfinkel !

PPCInstrVSX.td

 
 let UseVSXReg = 1, AddedComplexity = 400 in {
 let Predicates = [HasDirectMove] in {
   // VSX direct move instructions
   def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
                               "mfvsrd $rA, $XT", IIC_VecGeneral,
                               [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
       Requires<[In64BitMode]>;
+  let isCodeGenOnly = 1 in
+  def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vrrc:$XT),
+                             "mfvsrd $rA, $XT", IIC_VecGeneral,
+                             []>,
+      Requires<[In64BitMode]>;
   def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
                                "mfvsrwz $rA, $XT", IIC_VecGeneral,
                                [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
   def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
                               "mtvsrd $XT, $rA", IIC_VecGeneral,
                               [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
       Requires<[In64BitMode]>;
   def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
let Predicates = [IsISA3_0, HasDirectMove] in {
 
   def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT),
                               "mfvsrld $rA, $XT", IIC_VecGeneral,
                               []>, Requires<[In64BitMode]>;
 
 } // IsISA3_0, HasDirectMove
 } // UseVSXReg = 1
 
+// We want to parse this from asm, but we don't want to emit this as it would
+// be emitted with a VSX reg. So leave Emit = 0 here.
+def : InstAlias<"mfvrd $rA, $XT",
+                (MFVRD g8rc:$rA, vrrc:$XT), 0>;
+
 /*  Direct moves of various widths from GPR's into VSR's. Each move lines
     the value up into element 0 (both BE and LE). Namely, entities smaller than
     a doubleword are shifted left and moved for BE. For LE, they're moved, then
     swapped to go into the least significant element of the VSR.
 */
 def MovesToVSR {
   dag BE_BYTE_0 =
     (MTVSRD