TableGen: Fix infinite recursion in RegisterBankEmitter

[• tstellarAMD]

Summary

AMDGPU has two register classes with the same set of registers, and this
was causing this tablegen backend would get stuck in infinite recursion.

[dsanders]

It seems this patch removes ClassB from GPRRegBank:

const uint32_t GPRRegBankCoverageData[] = {
    // 0-31
    (1u << (MyTarget::ClassARegClassID - 0)) |
    0,
};

Was that the intention? If not, then I think we need to keep track of the classes that visitRegisterBankClasses() has been called on and prevent multiple visits at the top of visitRegisterBankClasses().

test/TableGen/RegisterBankEmitter.td

12

Could you add checks for the MyTarget::<Name>RegClassID's you're expecting here? I think you should have ClassB in GPRRegBank but this patch prevents ClassB from being added.

[dsanders]

Does the patch at https://reviews.llvm.org/D29178 fix your problem? It prevents visitRegisterBankClasses() visiting the same class more than once without changing the classes within each bank.

[• tstellarAMD]

Keep track of visited register class and make sure that equivalent register
classes are both added to the CoverageData.

[dsanders]

LGTM

test/TableGen/RegisterBankEmitter.td

+// RUN: llvm-tblgen -gen-register-bank -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def MyTarget : Target;
+def R0 : Register<"r0">;
+let Size = 32 in {
+  def ClassA : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
+  def ClassB : RegisterClass<"MyTarget", [i1], 32, (add ClassA)>;
+}
+
+// CHECK: GPRRegBankCoverageData
+// CHECK: MyTarget::ClassARegClassID
+// CHECK: MyTarget::ClassBRegClassID
+def GPRRegBank : RegisterBank<"GPR", [ClassA]>;

utils/TableGen/RegisterBankEmitter.cpp

 /// \param RC The register class to search.
 /// \param Kind A debug string containing the path the visitor took to reach RC.
 /// \param VisitFn The action to take for each class visited. It may be called
 ///                multiple times for a given class if there are multiple paths
 ///                to the class.
 static void visitRegisterBankClasses(
     CodeGenRegBank &RegisterClassHierarchy, const CodeGenRegisterClass *RC,
     const Twine Kind,
-    std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn) {
+    std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn,
+    SmallPtrSetImpl<const CodeGenRegisterClass *> &VisitedRCs) {
+
+  // Make sure we only visit each class once to avoid infinite loops.
+  if (VisitedRCs.count(RC))
+    return;
+  VisitedRCs.insert(RC);
+
   // Visit each explicitly named class.
   VisitFn(RC, Kind.str());
 
   for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {
     std::string TmpKind =
         (Twine(Kind) + " (" + PossibleSubclass.getName() + ")").str();
 
     // Visit each subclass of an explicitly named class.
     if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))
       visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass,
                                TmpKind + " " + RC->getName() + " subclass",
-                               VisitFn);
+                               VisitFn, VisitedRCs);
 
     // Visit each class that contains only subregisters of RC with a common
     // subregister-index.
     //
     // More precisely, PossibleSubclass is a subreg-class iff Reg:SubIdx is in
     // PossibleSubclass for all registers Reg from RC using any
     // subregister-index SubReg
     for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {

 void RegisterBankEmitter::run(raw_ostream &OS) {
   std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
   if (Targets.size() != 1)
     PrintFatalError("ERROR: Too many or too few subclasses of Target defined!");
   StringRef TargetName = Targets[0]->getName();
 
   std::vector<RegisterBank> Banks;
   for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {
+    SmallPtrSet<const CodeGenRegisterClass *, 8> VisitedRCs;
     RegisterBank Bank(*V);
 
     for (const CodeGenRegisterClass *RC :
          Bank.getExplictlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
       visitRegisterBankClasses(
           RegisterClassHierarchy, RC, "explicit",
           [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) {
             DEBUG(dbgs() << "Added " << RC->getName() << "(" << Kind << ")\n");
             Bank.addRegisterClass(RC);
-          });
+          }, VisitedRCs);
     }
 
     Banks.push_back(Bank);
   }
 
   emitSourceFileHeader("Register Bank Source Fragments", OS);
   OS << "#ifdef GET_REGBANK_DECLARATIONS\n"
      << "#undef GET_REGBANK_DECLARATIONS\n";