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TableGen: Fix infinite recursion in RegisterBankEmitter
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Authored by tstellarAMD on Jan 23 2017, 2:24 PM.

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Summary

AMDGPU has two register classes with the same set of registers, and this
was causing this tablegen backend would get stuck in infinite recursion.

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rL LLVM

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dsanders edited edge metadata.Jan 24 2017, 3:56 AM

It seems this patch removes ClassB from GPRRegBank:

const uint32_t GPRRegBankCoverageData[] = {
    // 0-31
    (1u << (MyTarget::ClassARegClassID - 0)) |
    0,
};

Was that the intention? If not, then I think we need to keep track of the classes that visitRegisterBankClasses() has been called on and prevent multiple visits at the top of visitRegisterBankClasses().

test/TableGen/RegisterBankEmitter.td
11 ↗(On Diff #85453)

Could you add checks for the MyTarget::<Name>RegClassID's you're expecting here? I think you should have ClassB in GPRRegBank but this patch prevents ClassB from being added.

Does the patch at https://reviews.llvm.org/D29178 fix your problem? It prevents visitRegisterBankClasses() visiting the same class more than once without changing the classes within each bank.

Keep track of visited register class and make sure that equivalent register
classes are both added to the CoverageData.

This revision is now accepted and ready to land.Jan 30 2017, 3:32 AM
This revision was automatically updated to reflect the committed changes.