[NDS32 3/46] Add stub backend

[shiva0217]

Summary

Add NDS32 TargetMachine class which specify data layout for NDS32 target
After this patch, NDS32 target could build successfully.

CMakeLists.txt

   Mips
   MSP430
   NVPTX
+  NDS32
   PowerPC
   RISCV
   Sparc

docs/CompilerWriterInfo.rst

 * `The XMOS XS1 Architecture (ISA) <https://www.xmos.com/en/download/public/The-XMOS-XS1-Architecture%28X7879A%29.pdf>`_
 * `Tools Development Guide (includes ABI) <https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf>`_
 
+NDS32
+------
+* `AndeStar ISA Manual (V3 ISA) <http://www.andestech.com/product.php?cls=9>`_
+* NOTE: This is an experimental porting of LLVM for AndeStar V3 ISA (NDS32 V3) of Andes Technology Corporation. Function-wise, correct code sequence is generated and it has passed key test suites. Performance-wise, there is NO target-specific optimization yet.
+
 Hexagon
 -------
 

lib/Target/LLVMBuild.txt

  Hexagon
  MSP430
  NVPTX
+ NDS32
  Mips
  PowerPC
  RISCV

lib/Target/NDS32/CMakeLists.txt

+add_llvm_target(NDS32CodeGen
+  NDS32TargetMachine.cpp
+  )

lib/Target/NDS32/LLVMBuild.txt

+;===- ./lib/Target/NDS32/LLVMBuild.txt ------------------------*- Conf -*---===;
+;
+;                     The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[common]
+subdirectories = TargetInfo
+
+[component_0]
+type = TargetGroup
+name = NDS32
+parent = Target
+
+[component_1]
+type = Library
+name = NDS32CodeGen
+parent = NDS32
+required_libraries = CodeGen Core NDS32Info Support Target
+add_to_library_groups = NDS32

lib/Target/NDS32/NDS32TargetMachine.h

+//===-- NDS32TargetMachine.h - Define TargetMachine for NDS32 -*- C++ -*---===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the NDS32 specific subclass of TargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+
+#ifndef LLVM_LIB_TARGET_NDS32_NDS32TARGETMACHINE_H
+#define LLVM_LIB_TARGET_NDS32_NDS32TARGETMACHINE_H
+
+#include "NDS32Subtarget.h"
+#include "llvm/Target/TargetFrameLowering.h"
+#include "llvm/Target/TargetMachine.h"
+
+namespace llvm {
+
+/// NDS32TargetMachine
+///
+class NDS32TargetMachine : public LLVMTargetMachine {
+
+protected:
+  std::unique_ptr<TargetLoweringObjectFile> TLOF;
+  NDS32Subtarget Subtarget;
+  mutable StringMap<std::unique_ptr<NDS32Subtarget>> SubtargetMap;
+
+
+public:
+  NDS32TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
+                     StringRef FS, const TargetOptions &Options,
+                     Optional<Reloc::Model> RM, CodeModel::Model CM,
+                     CodeGenOpt::Level OL);
+  ~NDS32TargetMachine() override;
+
+  const NDS32Subtarget *getSubtargetImpl() const { return &Subtarget; }
+  const NDS32Subtarget *getSubtargetImpl(const Function &F) const override;
+
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+
+  TargetLoweringObjectFile *getObjFileLowering() const override {
+    return TLOF.get();
+  }
+}; // NDS32TargetMachine.
+
+} // end namespace llvm
+
+#endif

lib/Target/NDS32/NDS32TargetMachine.cpp

+//===-- NDS32TargetMachine.cpp - Define TargetMachine for NDS32 -----------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Top-level implementation for the NDS32 target.
+//
+//===----------------------------------------------------------------------===//
+
+#include "NDS32TargetMachine.h"
+#include "NDS32.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/LegacyPassManager.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/Support/TargetRegistry.h"
+using namespace llvm;
+
+extern "C" void LLVMInitializeNDS32Target() {
+  // Register the target.
+  RegisterTargetMachine<NDS32TargetMachine> X(TheNDS32Target);
+}
+
+static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
+  if (!RM.hasValue())
+    return Reloc::Static;
+  return *RM;
+}
+
+static std::string computeDataLayout(const Triple &TT, StringRef CPU,
+                                     const TargetOptions &Options,
+                                     bool isLittle) {
+  std::string Ret = "";
+
+  if (isLittle)
+    // Little endian.
+    Ret += "e";
+  else
+    // Big endian.
+    Ret += "E";
+
+  //ELF mangling of names is enabled
+  Ret += "-m:e";
+
+  // Pointers are 32 bits and aligned to 32 bits.
+  Ret += "-p:32:32";
+
+  // 64 bit integers with natural alignment.
+  Ret += "-i64:64";
+
+  // Try to align aggregates to 32 bits
+  Ret += "-a:0:32";
+
+  // Integer registers are 32 bits.
+  Ret += "-n32";
+
+   // The stack is 64 bit aligned
+  Ret += "-S64";
+
+  return Ret;
+}
+
+NDS32TargetMachine::NDS32TargetMachine(const Target &T, const Triple &TT,
+                                       StringRef CPU, StringRef FS,
+                                       const TargetOptions &Options,
+                                       Optional<Reloc::Model> RM,
+                                       CodeModel::Model CM,
+                                       CodeGenOpt::Level OL)
+    : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, true),
+                        TT, CPU, FS, Options, getEffectiveRelocModel(RM),
+                        CM, OL),
+      TLOF(make_unique<TargetLoweringObjectFileELF>()),
+      Subtarget(TT, CPU, FS, *this) {
+  initAsmInfo();
+}
+
+NDS32TargetMachine::~NDS32TargetMachine() {}
+
+const NDS32Subtarget *
+NDS32TargetMachine::getSubtargetImpl(const Function &F) const {
+  Attribute CPUAttr = F.getFnAttribute("target-cpu");
+  Attribute FSAttr = F.getFnAttribute("target-features");
+
+  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
+                        ? CPUAttr.getValueAsString().str()
+                        : TargetCPU;
+  std::string FS = !FSAttr.hasAttribute(Attribute::None)
+                       ? FSAttr.getValueAsString().str()
+                       : TargetFS;
+
+  auto &I = SubtargetMap[CPU + FS];
+  if (!I) {
+    // This needs to be done before we create a new subtarget since any
+    // creation will depend on the TM and the code generation flags on the
+    // function that reside in TargetOptions.
+    resetTargetOptions(F);
+    I = llvm::make_unique<NDS32Subtarget>(TargetTriple, CPU, FS, *this);
+  }
+  return I.get();
+}
+
+namespace {
+/// NDS32 Code Generator Pass Configuration Options.
+class NDS32PassConfig : public TargetPassConfig {
+public:
+  NDS32PassConfig(NDS32TargetMachine *TM, PassManagerBase &PM)
+    : TargetPassConfig(TM, PM) {}
+
+  NDS32TargetMachine &getNDS32TargetMachine() const {
+    return getTM<NDS32TargetMachine>();
+  }
+};
+} // namespace
+
+TargetPassConfig *NDS32TargetMachine::createPassConfig(PassManagerBase &PM) {
+  return new NDS32PassConfig(this, PM);
+}