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Differential D28065

AMDGPU: Fix shrinking of addc/subb.
ClosedPublic

Authored by arsenm on Dec 22 2016, 1:14 PM.

Details

Reviewers
• tstellarAMD
nhaehnle
Summary

To shrink to VOP2 the input carry must also be VCC.

Diff Detail

Event Timeline

arsenm updated this revision to Diff 82363.Dec 22 2016, 1:14 PM
arsenm retitled this revision from to AMDGPU: Fix shrinking of addc/subb..
arsenm updated this object.
arsenm added a subscriber: llvm-commits.
Herald added a reviewer: • tstellarAMD. · View Herald TranscriptDec 22 2016, 1:14 PM
Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others. · View Herald Transcript
arsenm added a comment.Jan 3 2017, 2:36 PM

ping

nhaehnle accepted this revision.Jan 11 2017, 12:53 PM
nhaehnle added a reviewer: nhaehnle.

LGTM

This revision is now accepted and ready to land.Jan 11 2017, 12:53 PM
arsenm closed this revision.Jan 11 2017, 3:09 PM

r291720

Revision Contents

PathSize
lib/
Target/
AMDGPU/
32 lines
test/
CodeGen/
AMDGPU/
292 lines

Diff 82363

lib/Target/AMDGPU/SIShrinkInstructions.cpp

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Linesstatic bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
// a special case for it. It can only be shrunk if the third operand // a special case for it. It can only be shrunk if the third operand
// is vcc. We should handle this the same way we handle vopc, by addding // is vcc. We should handle this the same way we handle vopc, by addding
// a register allocation hint pre-regalloc and then do the shrinking // a register allocation hint pre-regalloc and then do the shrinking
// post-regalloc. // post-regalloc.
if (Src2) { if (Src2) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
default: return false; default: return false;
case AMDGPU::V_ADDC_U32_e64:
case AMDGPU::V_SUBB_U32_e64:
// Additional verification is needed for sdst/src2.
return true;
case AMDGPU::V_MAC_F32_e64: case AMDGPU::V_MAC_F32_e64:
case AMDGPU::V_MAC_F16_e64: case AMDGPU::V_MAC_F16_e64:
if (!isVGPR(Src2, TRI, MRI) || if (!isVGPR(Src2, TRI, MRI) ||
TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers)) TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
return false; return false;
break; break;
case AMDGPU::V_CNDMASK_B32_e64: case AMDGPU::V_CNDMASK_B32_e64:
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
} }
// Copy MachineOperand with all flags except setting it as implicit. // Copy MachineOperand with all flags except setting it as implicit.
static void copyFlagsToImplicitVCC(MachineInstr &MI, static void copyFlagsToImplicitVCC(MachineInstr &MI,
const MachineOperand &Orig) { const MachineOperand &Orig) {
for (MachineOperand &Use : MI.implicit_operands()) { for (MachineOperand &Use : MI.implicit_operands()) {
if (Use.getReg() == AMDGPU::VCC) { if (Use.isUse() && Use.getReg() == AMDGPU::VCC) {
Use.setIsUndef(Orig.isUndef()); Use.setIsUndef(Orig.isUndef());
Use.setIsKill(Orig.isKill()); Use.setIsKill(Orig.isKill());
return; return;
} }
} }
} }
static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) {
▲ Show 20 Lines • Show All 268 Lines • ▼ Show 20 Lines for (I = MBB.begin(); I != MBB.end(); I = Next) {
} }
if (SReg != AMDGPU::VCC) if (SReg != AMDGPU::VCC)
continue; continue;
} }
// Check for the bool flag output for instructions like V_ADD_I32_e64. // Check for the bool flag output for instructions like V_ADD_I32_e64.
const MachineOperand *SDst = TII->getNamedOperand(MI, const MachineOperand *SDst = TII->getNamedOperand(MI,
AMDGPU::OpName::sdst); AMDGPU::OpName::sdst);
if (SDst && SDst->getReg() != AMDGPU::VCC) {
// Check the carry-in operand for v_addc_u32_e64.
const MachineOperand *Src2 = TII->getNamedOperand(MI,
AMDGPU::OpName::src2);
if (SDst) {
if (SDst->getReg() != AMDGPU::VCC) {
if (TargetRegisterInfo::isVirtualRegister(SDst->getReg())) if (TargetRegisterInfo::isVirtualRegister(SDst->getReg()))
MRI.setRegAllocationHint(SDst->getReg(), 0, AMDGPU::VCC); MRI.setRegAllocationHint(SDst->getReg(), 0, AMDGPU::VCC);
continue;
}
// All of the instructions with carry outs also have an SGPR input in
// src2.
if (Src2 && Src2->getReg() != AMDGPU::VCC) {
if (TargetRegisterInfo::isVirtualRegister(Src2->getReg()))
MRI.setRegAllocationHint(Src2->getReg(), 0, AMDGPU::VCC);
continue; continue;
} }
}
// We can shrink this instruction // We can shrink this instruction
DEBUG(dbgs() << "Shrinking " << MI); DEBUG(dbgs() << "Shrinking " << MI);
MachineInstrBuilder Inst32 = MachineInstrBuilder Inst32 =
BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32)); BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32));
// Add the dst operand if the 32-bit encoding also has an explicit $vdst. // Add the dst operand if the 32-bit encoding also has an explicit $vdst.
Show All 10 Lines for (I = MBB.begin(); I != MBB.end(); I = Next) {
Inst32.addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::src0)); Inst32.addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::src0));
const MachineOperand *Src1 = const MachineOperand *Src1 =
TII->getNamedOperand(MI, AMDGPU::OpName::src1); TII->getNamedOperand(MI, AMDGPU::OpName::src1);
if (Src1) if (Src1)
Inst32.addOperand(*Src1); Inst32.addOperand(*Src1);
const MachineOperand *Src2 =
TII->getNamedOperand(MI, AMDGPU::OpName::src2);
if (Src2) { if (Src2) {
int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2); int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);
if (Op32Src2Idx != -1) { if (Op32Src2Idx != -1) {
Inst32.addOperand(*Src2); Inst32.addOperand(*Src2);
} else { } else {
// In the case of V_CNDMASK_B32_e32, the explicit operand src2 is // In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
// replaced with an implicit read of vcc. This was already added // replaced with an implicit read of vcc. This was already added
// during the initial BuildMI, so find it to preserve the flags. // during the initial BuildMI, so find it to preserve the flags.
Show All 19 Lines

test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir

Show All 40 Lines define void @shrink_subrev_vop3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 %tid.ext
%a = load volatile i32, i32 addrspace(1)* %a.ptr %a = load volatile i32, i32 addrspace(1)* %a.ptr
%b = load volatile i32, i32 addrspace(1)* %b.ptr %b = load volatile i32, i32 addrspace(1)* %b.ptr
%result = sub i32 %a, %b %result = sub i32 %a, %b
store volatile i32 %result, i32 addrspace(1)* %out.gep store volatile i32 %result, i32 addrspace(1)* %out.gep
ret void ret void
} }
define void @check_addc_src2_vop3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.ptr = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext
%b.ptr = getelementptr i32, i32 addrspace(1)* %a.ptr, i32 1
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 %tid.ext
%a = load volatile i32, i32 addrspace(1)* %a.ptr
%b = load volatile i32, i32 addrspace(1)* %b.ptr
%result = add i32 %a, %b
store volatile i32 %result, i32 addrspace(1)* %out.gep
ret void
}
define void @shrink_addc_vop3(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.ptr = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext
%b.ptr = getelementptr i32, i32 addrspace(1)* %a.ptr, i32 1
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 %tid.ext
%a = load volatile i32, i32 addrspace(1)* %a.ptr
%b = load volatile i32, i32 addrspace(1)* %b.ptr
%result = add i32 %a, %b
store volatile i32 %result, i32 addrspace(1)* %out.gep
ret void
}
define void @shrink_addc_undef_vcc(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.ptr = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext
%b.ptr = getelementptr i32, i32 addrspace(1)* %a.ptr, i32 1
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 %tid.ext
%a = load volatile i32, i32 addrspace(1)* %a.ptr
%b = load volatile i32, i32 addrspace(1)* %b.ptr
%result = add i32 %a, %b
store volatile i32 %result, i32 addrspace(1)* %out.gep
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
... ...
--- ---
# GCN-LABEL: name: shrink_add_vop3{{$}} # GCN-LABEL: name: shrink_add_vop3{{$}}
▲ Show 20 Lines • Show All 241 Lines • ▼ Show 20 Lines bb.0 (%ir-block.0):
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from %ir.a.ptr) %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from %ir.a.ptr)
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec :: (volatile load 4 from %ir.b.ptr) %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec :: (volatile load 4 from %ir.b.ptr)
%29, %9 = V_SUBREV_I32_e64 %19, %17, implicit %exec %29, %9 = V_SUBREV_I32_e64 %19, %17, implicit %exec
%24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
BUFFER_STORE_DWORD_ADDR64 %29, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into %ir.out.gep) BUFFER_STORE_DWORD_ADDR64 %29, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into %ir.out.gep)
S_ENDPGM S_ENDPGM
... ...
---
# GCN-LABEL: name: check_addc_src2_vop3{{$}}
# GCN: %29, %vcc = V_ADDC_U32_e64 %19, %17, %9, implicit %exec
# GCN: %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
name: check_addc_src2_vop3
alignment: 0
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: sgpr_64 }
- { id: 1, class: sreg_32_xm0 }
- { id: 2, class: sgpr_32 }
- { id: 3, class: vgpr_32 }
- { id: 4, class: sreg_64_xexec }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: sreg_32 }
- { id: 7, class: sreg_32 }
- { id: 8, class: sreg_32_xm0 }
- { id: 9, class: sreg_64 }
- { id: 10, class: sreg_32_xm0 }
- { id: 11, class: sreg_32_xm0 }
- { id: 12, class: sgpr_64 }
- { id: 13, class: sgpr_128 }
- { id: 14, class: sreg_32_xm0 }
- { id: 15, class: sreg_64 }
- { id: 16, class: sgpr_128 }
- { id: 17, class: vgpr_32 }
- { id: 18, class: vreg_64 }
- { id: 19, class: vgpr_32 }
- { id: 20, class: vreg_64 }
- { id: 21, class: sreg_32_xm0 }
- { id: 22, class: sreg_32 }
- { id: 23, class: sreg_32 }
- { id: 24, class: vgpr_32 }
- { id: 25, class: vreg_64 }
- { id: 26, class: vgpr_32 }
- { id: 27, class: vreg_64 }
- { id: 28, class: vreg_64 }
- { id: 29, class: vgpr_32 }
liveins:
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '%vgpr0', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0 (%ir-block.0):
liveins: %sgpr0_sgpr1, %vgpr0
%3 = COPY %vgpr0
%0 = COPY %sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
%26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
%27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440
%11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18
%28 = V_LSHL_B64 killed %27, 2, implicit %exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from %ir.a.ptr)
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec :: (volatile load 4 from %ir.b.ptr)
%9 = S_MOV_B64 0
%29, %vcc = V_ADDC_U32_e64 %19, %17, %9, implicit %exec
%24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into %ir.out.gep)
S_ENDPGM
...
---
# GCN-LABEL: name: shrink_addc_vop3{{$}}
# GCN: %29 = V_ADDC_U32_e32 %17, %19, implicit-def %vcc, implicit %vcc, implicit %exec
# GCN %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
name: shrink_addc_vop3
alignment: 0
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: sgpr_64 }
- { id: 1, class: sreg_32_xm0 }
- { id: 2, class: sgpr_32 }
- { id: 3, class: vgpr_32 }
- { id: 4, class: sreg_64_xexec }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: sreg_32 }
- { id: 7, class: sreg_32 }
- { id: 8, class: sreg_32_xm0 }
- { id: 9, class: sreg_64 }
- { id: 10, class: sreg_32_xm0 }
- { id: 11, class: sreg_32_xm0 }
- { id: 12, class: sgpr_64 }
- { id: 13, class: sgpr_128 }
- { id: 14, class: sreg_32_xm0 }
- { id: 15, class: sreg_64 }
- { id: 16, class: sgpr_128 }
- { id: 17, class: vgpr_32 }
- { id: 18, class: vreg_64 }
- { id: 19, class: vgpr_32 }
- { id: 20, class: vreg_64 }
- { id: 21, class: sreg_32_xm0 }
- { id: 22, class: sreg_32 }
- { id: 23, class: sreg_32 }
- { id: 24, class: vgpr_32 }
- { id: 25, class: vreg_64 }
- { id: 26, class: vgpr_32 }
- { id: 27, class: vreg_64 }
- { id: 28, class: vreg_64 }
- { id: 29, class: vgpr_32 }
liveins:
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '%vgpr0', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0 (%ir-block.0):
liveins: %sgpr0_sgpr1, %vgpr0
%3 = COPY %vgpr0
%0 = COPY %sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
%26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
%27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440
%11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18
%28 = V_LSHL_B64 killed %27, 2, implicit %exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from %ir.a.ptr)
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec :: (volatile load 4 from %ir.b.ptr)
%vcc = S_MOV_B64 0
%29, %vcc = V_ADDC_U32_e64 %19, %17, %vcc, implicit %exec
%24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into %ir.out.gep)
S_ENDPGM
...
---
# GCN-LABEL: name: shrink_addc_undef_vcc{{$}}
# GCN: %29 = V_ADDC_U32_e32 %17, %19, implicit-def %vcc, implicit undef %vcc, implicit %exec
# GCN: %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
name: shrink_addc_undef_vcc
alignment: 0
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: sgpr_64 }
- { id: 1, class: sreg_32_xm0 }
- { id: 2, class: sgpr_32 }
- { id: 3, class: vgpr_32 }
- { id: 4, class: sreg_64_xexec }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: sreg_32 }
- { id: 7, class: sreg_32 }
- { id: 8, class: sreg_32_xm0 }
- { id: 9, class: sreg_64 }
- { id: 10, class: sreg_32_xm0 }
- { id: 11, class: sreg_32_xm0 }
- { id: 12, class: sgpr_64 }
- { id: 13, class: sgpr_128 }
- { id: 14, class: sreg_32_xm0 }
- { id: 15, class: sreg_64 }
- { id: 16, class: sgpr_128 }
- { id: 17, class: vgpr_32 }
- { id: 18, class: vreg_64 }
- { id: 19, class: vgpr_32 }
- { id: 20, class: vreg_64 }
- { id: 21, class: sreg_32_xm0 }
- { id: 22, class: sreg_32 }
- { id: 23, class: sreg_32 }
- { id: 24, class: vgpr_32 }
- { id: 25, class: vreg_64 }
- { id: 26, class: vgpr_32 }
- { id: 27, class: vreg_64 }
- { id: 28, class: vreg_64 }
- { id: 29, class: vgpr_32 }
liveins:
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
- { reg: '%vgpr0', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0 (%ir-block.0):
liveins: %sgpr0_sgpr1, %vgpr0
%3 = COPY %vgpr0
%0 = COPY %sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
%26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
%27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440
%11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18
%28 = V_LSHL_B64 killed %27, 2, implicit %exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from %ir.a.ptr)
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec :: (volatile load 4 from %ir.b.ptr)
%29, %vcc = V_ADDC_U32_e64 %19, %17, undef %vcc, implicit %exec
%24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into %ir.out.gep)
S_ENDPGM
...