AMDGPU: Fix i128 mul

[• tstellarAMD]

LGTM.

[arsenm]

r289231

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

if (VT == MVT::i16)
     LC = RTLIB::MUL_I16;
   else if (VT == MVT::i32)
     LC = RTLIB::MUL_I32;
   else if (VT == MVT::i64)
     LC = RTLIB::MUL_I64;
   else if (VT == MVT::i128)
     LC = RTLIB::MUL_I128;
 
-  if (LC == RTLIB::UNKNOWN_LIBCALL) {
+  if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(LC)) {
     // We'll expand the multiplication by brute force because we have no other
     // options. This is a trivially-generalized version of the code from
     // Hacker's Delight (itself derived from Knuth's Algorithm M from section
     // 4.3.1).
     unsigned Bits = NVT.getSizeInBits();
     unsigned HalfBits = Bits >> 1;
     SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(Bits, HalfBits), dl,
                                    NVT);

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
   // bit operations. This is in general better, but the alternative using BFI
   // instructions may be better if the select sources are SGPRs.
   setOperationAction(ISD::SELECT, MVT::v2f32, Promote);
   AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32);
 
   setOperationAction(ISD::SELECT, MVT::v4f32, Promote);
   AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
 
+  // There are no libcalls of any kind.
+  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I)
+    setLibcallName(static_cast<RTLIB::Libcall>(I), nullptr);
+
   setBooleanContents(ZeroOrNegativeOneBooleanContent);
   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
 
   setSchedulingPreference(Sched::RegPressure);
   setJumpIsExpensive(true);
   setHasMultipleConditionRegisters(true);
 
   // SI at least has hardware support for floating point exceptions, but no way

test/CodeGen/AMDGPU/mul.ll

else:
   %2 = mul i64 %a, %b
   br label %endif
 
 endif:
   %3 = phi i64 [%1, %if], [%2, %else]
   store i64 %3, i64 addrspace(1)* %out
   ret void
 }
+
+; FIXME: Load dwordx4
+; FUNC-LABEL: {{^}}s_mul_i128:
+; SI: s_load_dwordx2
+; SI: s_load_dwordx2
+; SI: s_load_dwordx2
+; SI: s_load_dwordx2
+
+
+; SI: v_mul_hi_u32
+; SI: v_mul_hi_u32
+; SI: s_mul_i32
+; SI: v_mul_hi_u32
+; SI: s_mul_i32
+; SI: s_mul_i32
+; SI: v_mul_hi_u32
+; SI: v_mul_hi_u32
+; SI: s_mul_i32
+; SI-DAG: s_mul_i32
+; SI-DAG: v_mul_hi_u32
+; SI: s_mul_i32
+; SI: s_mul_i32
+; SI: s_mul_i32
+; SI: s_mul_i32
+; SI: s_mul_i32
+
+; SI: buffer_store_dwordx4
+define void @s_mul_i128(i128 addrspace(1)* %out, i128 %a, i128 %b) nounwind #0 {
+  %mul = mul i128 %a, %b
+  store i128 %mul, i128 addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}v_mul_i128:
+; SI: {{buffer|flat}}_load_dwordx4
+; SI: {{buffer|flat}}_load_dwordx4
+
+; SI: v_mul_lo_i32
+; SI: v_mul_hi_u32
+; SI: v_mul_hi_u32
+; SI: v_mul_lo_i32
+; SI: v_mul_hi_u32
+; SI: v_mul_hi_u32
+; SI: v_mul_lo_i32
+; SI: v_mul_lo_i32
+; SI: v_add_i32_e32
+; SI: v_mul_hi_u32
+; SI: v_mul_lo_i32
+; SI: v_mul_hi_u32
+; SI: v_mul_lo_i32
+; SI: v_mul_lo_i32
+; SI: v_mul_lo_i32
+; SI: v_mul_lo_i32
+; SI: v_mul_lo_i32
+
+; SI: {{buffer|flat}}_store_dwordx4
+define void @v_mul_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %aptr, i128 addrspace(1)* %bptr) #0 {
+  %tid = call i32 @llvm.r600.read.tidig.x()
+  %gep.a = getelementptr inbounds i128, i128 addrspace(1)* %aptr, i32 %tid
+  %gep.b = getelementptr inbounds i128, i128 addrspace(1)* %bptr, i32 %tid
+  %gep.out = getelementptr inbounds i128, i128 addrspace(1)* %bptr, i32 %tid
+  %a = load i128, i128 addrspace(1)* %gep.a
+  %b = load i128, i128 addrspace(1)* %gep.b
+  %mul = mul i128 %a, %b
+  store i128 %mul, i128 addrspace(1)* %gep.out
+  ret void
+}
+
+declare i32 @llvm.r600.read.tidig.x() #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone}