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Differential D27423

AMDGPU: Select i16 instructions to VOP3 forms
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Authored by arsenm on Dec 5 2016, 11:37 AM.

Details

Reviewers
• tstellarAMD
Summary

These were selecting directly to the VOP2 form instead
of VOP3 like the i32 instructions. Fixes regressions in
future commits where an immediate isn't folded because it was
initially used for the second operand.




Because uniform 16-bit operations are promoted to i32, it's

 difficult to get a simple testcase where this matters.
Diff Detail
Event Timeline
arsenm updated this revision to Diff 80301.Dec 5 2016, 11:37 AM
arsenm retitled this revision from  to AMDGPU: Select i16 instructions to VOP3 forms.
arsenm updated this object.
arsenm added a subscriber: llvm-commits.
Herald added a reviewer: • tstellarAMD.  ·  View Herald TranscriptDec 5 2016, 11:37 AM
Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others.  ·  View Herald Transcript
• tstellarAMD accepted this revision.Dec 5 2016, 5:55 PM
• tstellarAMD edited edge metadata.
LGTM.
This revision is now accepted and ready to land.Dec 5 2016, 5:55 PM
arsenm closed this revision.Dec 8 2016, 10:29 PM
r289189
Revision Contents
PathSize
lib/
Target/
AMDGPU/
20 lines
test/
CodeGen/
AMDGPU/
10 lines
Diff 80301
lib/Target/AMDGPU/VOP2Instructions.td
Show First 20 Lines • Show All 412 Lines • ▼ Show 20 Lines



class ZExt_i16_i1_Pat <SDNode ext> : Pat <
class ZExt_i16_i1_Pat <SDNode ext> : Pat <

  (i16 (ext i1:$src)),
  (i16 (ext i1:$src)),

  (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src)
  (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src)

>;
>;




let Predicates = [isVI] in {
let Predicates = [isVI] in {




defm : Arithmetic_i16_Pats<add, V_ADD_U16_e32>;
defm : Arithmetic_i16_Pats<add, V_ADD_U16_e64>;

defm : Arithmetic_i16_Pats<mul, V_MUL_LO_U16_e32>;
defm : Arithmetic_i16_Pats<mul, V_MUL_LO_U16_e64>;

defm : Arithmetic_i16_Pats<sub, V_SUB_U16_e32>;
defm : Arithmetic_i16_Pats<sub, V_SUB_U16_e64>;

defm : Arithmetic_i16_Pats<smin, V_MIN_I16_e32>;
defm : Arithmetic_i16_Pats<smin, V_MIN_I16_e64>;

defm : Arithmetic_i16_Pats<smax, V_MAX_I16_e32>;
defm : Arithmetic_i16_Pats<smax, V_MAX_I16_e64>;

defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e32>;
defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e64>;

defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e32>;
defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e64>;




def : Pat <
def : Pat <

  (and i16:$src0, i16:$src1),
  (and i16:$src0, i16:$src1),

  (V_AND_B32_e32 $src0, $src1)
  (V_AND_B32_e64 $src0, $src1)

>;
>;




def : Pat <
def : Pat <

  (or i16:$src0, i16:$src1),
  (or i16:$src0, i16:$src1),

  (V_OR_B32_e32 $src0, $src1)
  (V_OR_B32_e64 $src0, $src1)

>;
>;




def : Pat <
def : Pat <

  (xor i16:$src0, i16:$src1),
  (xor i16:$src0, i16:$src1),

  (V_XOR_B32_e32 $src0, $src1)
  (V_XOR_B32_e64 $src0, $src1)

>;
>;




defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e32>;
defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e32>;

defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e32>;
defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e32>;

defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_B16_e32>;
defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_B16_e32>;




def : ZExt_i16_i1_Pat<zext>;
def : ZExt_i16_i1_Pat<zext>;

def : ZExt_i16_i1_Pat<anyext>;
def : ZExt_i16_i1_Pat<anyext>;

▲ Show 20 Lines • Show All 270 Lines • Show Last 20 Lines
test/CodeGen/AMDGPU/add.i16.ll
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s




; FIXME: Need to handle non-uniform case for function below (load without gep).
; FIXME: Need to handle non-uniform case for function below (load without gep).

; GCN-LABEL: {{^}}v_test_add_i16:
; GCN-LABEL: {{^}}v_test_add_i16:

; VI: flat_load_ushort [[A:v[0-9]+]]
; VI: flat_load_ushort [[A:v[0-9]+]]

; VI: flat_load_ushort [[B:v[0-9]+]]
; VI: flat_load_ushort [[B:v[0-9]+]]

; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[B]], [[A]]

; VI-NEXT: buffer_store_short [[ADD]]
; VI-NEXT: buffer_store_short [[ADD]]

define void @v_test_add_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
define void @v_test_add_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid
  %gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid

  %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
  %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid

  %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
  %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid

  %a = load volatile i16, i16 addrspace(1)* %gep.in0
  %a = load volatile i16, i16 addrspace(1)* %gep.in0

  %b = load volatile i16, i16 addrspace(1)* %gep.in1
  %b = load volatile i16, i16 addrspace(1)* %gep.in1

▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Linesdefine void @v_test_add_i16_inline_neg1(i16 addrspace(1)* %out, i16 addrspace(1)* %in0) #1 {

  store i16 %add, i16 addrspace(1)* %out
  store i16 %add, i16 addrspace(1)* %out

  ret void
  ret void

}
}




; FIXME: Need to handle non-uniform case for function below (load without gep).
; FIXME: Need to handle non-uniform case for function below (load without gep).

; GCN-LABEL: {{^}}v_test_add_i16_zext_to_i32:
; GCN-LABEL: {{^}}v_test_add_i16_zext_to_i32:

; VI: flat_load_ushort [[A:v[0-9]+]]
; VI: flat_load_ushort [[A:v[0-9]+]]

; VI: flat_load_ushort [[B:v[0-9]+]]
; VI: flat_load_ushort [[B:v[0-9]+]]

; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[B]], [[A]]

; VI-NEXT: buffer_store_dword [[ADD]]
; VI-NEXT: buffer_store_dword [[ADD]]

define void @v_test_add_i16_zext_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
define void @v_test_add_i16_zext_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
  %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid

  %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
  %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid

  %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
  %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid

  %a = load volatile i16, i16 addrspace(1)* %gep.in0
  %a = load volatile i16, i16 addrspace(1)* %gep.in0

  %b = load volatile i16, i16 addrspace(1)* %gep.in1
  %b = load volatile i16, i16 addrspace(1)* %gep.in1

  %add = add i16 %a, %b
  %add = add i16 %a, %b

  %ext = zext i16 %add to i32
  %ext = zext i16 %add to i32

  store i32 %ext, i32 addrspace(1)* %out
  store i32 %ext, i32 addrspace(1)* %out

  ret void
  ret void

}
}




; FIXME: Need to handle non-uniform case for function below (load without gep).
; FIXME: Need to handle non-uniform case for function below (load without gep).

; GCN-LABEL: {{^}}v_test_add_i16_zext_to_i64:
; GCN-LABEL: {{^}}v_test_add_i16_zext_to_i64:

; VI: flat_load_ushort [[A:v[0-9]+]]
; VI: flat_load_ushort [[A:v[0-9]+]]

; VI: flat_load_ushort [[B:v[0-9]+]]
; VI: flat_load_ushort [[B:v[0-9]+]]

; VI-DAG: v_add_u16_e32 v[[ADD:[0-9]+]], [[A]], [[B]]
; VI-DAG: v_add_u16_e32 v[[ADD:[0-9]+]], [[B]], [[A]]

; VI-DAG: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0
; VI-DAG: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0

; VI: buffer_store_dwordx2 v{{\[}}[[ADD]]:[[VZERO]]{{\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
; VI: buffer_store_dwordx2 v{{\[}}[[ADD]]:[[VZERO]]{{\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}

define void @v_test_add_i16_zext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
define void @v_test_add_i16_zext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid
  %gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid

  %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
  %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid

  %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
  %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid

  %a = load volatile i16, i16 addrspace(1)* %gep.in0
  %a = load volatile i16, i16 addrspace(1)* %gep.in0

  %b = load volatile i16, i16 addrspace(1)* %gep.in1
  %b = load volatile i16, i16 addrspace(1)* %gep.in1

  %add = add i16 %a, %b
  %add = add i16 %a, %b

  %ext = zext i16 %add to i64
  %ext = zext i16 %add to i64

  store i64 %ext, i64 addrspace(1)* %out
  store i64 %ext, i64 addrspace(1)* %out

  ret void
  ret void

}
}




; FIXME: Need to handle non-uniform case for function below (load without gep).
; FIXME: Need to handle non-uniform case for function below (load without gep).

; GCN-LABEL: {{^}}v_test_add_i16_sext_to_i32:
; GCN-LABEL: {{^}}v_test_add_i16_sext_to_i32:

; VI: flat_load_ushort [[A:v[0-9]+]]
; VI: flat_load_ushort [[A:v[0-9]+]]

; VI: flat_load_ushort [[B:v[0-9]+]]
; VI: flat_load_ushort [[B:v[0-9]+]]

; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
; VI: v_add_u16_e32 [[ADD:v[0-9]+]],  [[B]], [[A]]

; VI-NEXT: v_bfe_i32 [[SEXT:v[0-9]+]], [[ADD]], 0, 16
; VI-NEXT: v_bfe_i32 [[SEXT:v[0-9]+]], [[ADD]], 0, 16

; VI-NEXT: buffer_store_dword [[SEXT]]
; VI-NEXT: buffer_store_dword [[SEXT]]

define void @v_test_add_i16_sext_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
define void @v_test_add_i16_sext_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
  %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid

  %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
  %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid

  %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
  %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid

  %a = load i16, i16 addrspace(1)* %gep.in0
  %a = load i16, i16 addrspace(1)* %gep.in0

  %b = load i16, i16 addrspace(1)* %gep.in1
  %b = load i16, i16 addrspace(1)* %gep.in1

  %add = add i16 %a, %b
  %add = add i16 %a, %b

  %ext = sext i16 %add to i32
  %ext = sext i16 %add to i32

  store i32 %ext, i32 addrspace(1)* %out
  store i32 %ext, i32 addrspace(1)* %out

  ret void
  ret void

}
}




; FIXME: Need to handle non-uniform case for function below (load without gep).
; FIXME: Need to handle non-uniform case for function below (load without gep).

; GCN-LABEL: {{^}}v_test_add_i16_sext_to_i64:
; GCN-LABEL: {{^}}v_test_add_i16_sext_to_i64:

; VI: flat_load_ushort [[A:v[0-9]+]]
; VI: flat_load_ushort [[A:v[0-9]+]]

; VI: flat_load_ushort [[B:v[0-9]+]]
; VI: flat_load_ushort [[B:v[0-9]+]]

; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[B]], [[A]]

; VI-NEXT: v_bfe_i32 v[[LO:[0-9]+]], [[ADD]], 0, 16
; VI-NEXT: v_bfe_i32 v[[LO:[0-9]+]], [[ADD]], 0, 16

; VI-NEXT: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; VI-NEXT: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]

; VI-NEXT: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
; VI-NEXT: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}

define void @v_test_add_i16_sext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
define void @v_test_add_i16_sext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {

  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %tid = call i32 @llvm.amdgcn.workitem.id.x()

  %gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid
  %gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid

  %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
  %gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid

  %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
  %gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid

Show All 12 Lines